Controlling gate formation for high density cell layout

A method of forming a semiconductor structure, the method comprising:

• forming a gate dielectric layer over a substrate;
• forming a gate electrode layer over the gate dielectric layer;
• etching the gate electrode layer and the gate dielectric layer to form a horizontal gate structure and a vertical gate structure, wherein the horizontal gate structure and the vertical gate structure are connected by an interconnection portion;
• forming a photoresist covering the horizontal gate structure and the vertical gate structure, the photoresist having a gap exposing the interconnection portion between the horizontal gate structure and the vertical gate structure;
• etching the interconnection portion;
• forming an anti-reflective coating (ARC) over the gate electrode layer before the horizontal gate structure and the vertical gate structure are formed;
• removing the photoresist;
• and
• removing the ARC after the photoresist is removed;
• wherein etching the gate electrode layer and the gate dielectric layer includes forming a dummy gate;
• wherein forming the photoresist includes forming the photoresist to have a further gap exposing the dummy gate;
• and
• wherein etching the interconnection portion includes etching the dummy gate.

A method of forming a semiconductor structure, the method comprising:

• providing a semiconductor substrate comprising:
• a first active region;
• a second active region;
• and
• an insulating region separating the first and the second active regions;
• forming a vertical gate structure extending over the first and the second active regions and the insulating region;
• forming a horizontal gate structure extending over the insulating region between the first and the second active regions, wherein the horizontal gate structure and the vertical gate structure are connected by an interconnection portion;
• forming a photoresist having a first portion and a second portion, wherein the first portion of the photoresist covers a portion of the vertical gate structure, and the second portion of the photoresist covers the horizontal gate structure, wherein the first and the second portions of the photoresist have a gap exposing the interconnection portion directly over the insulating region;
• and
• etching the interconnection portion exposed through the gap;
• wherein the forming the vertical gate structure includes forming a dummy pattern;
• wherein forming the photoresist includes forming the photoresist to have a further gap exposing the dummy pattern;
• and
• wherein etching the interconnection portion includes etching the dummy pattern.