Active matrix substrate, display panel, and display device
AssigneeSharp Kabushiki Kaisha
InventorsHiromitsu Katsui, Yoshimasa Chikama, Wataru Nakamura, Tetsunori Tanaka, Kenichi Kitoh
Life of this patent
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Abstract
A drain electrode (17) includes (i) a lower drain electrode (17a) stacked on a semiconductor layer (14) so as to partially cover an upper surface of the semiconductor layer (14) and (ii) an upper drain electrode (17b). The semiconductor layer (14), the lower drain electrode (17a), and the upper drain electrode (17b) form steps. In a step part where the steps are formed, a distance between a periphery of the lower drain electrode (17a) and a periphery of the upper drain electrode (17b) is more than 0.4 μm but less than 1.5 μm.
Claims7
An active matrix substrate, comprising:
- thin film transistors each of which includes (i) a semiconductor layer including a channel layer and (ii) a signal electrode and a drain electrode, each of which is electrically connected to the semiconductor layer, wherein
- the signal electrode includes (i) a first signal metal layer stacked directly on the semiconductor layer so as to partially cover an upper surface of the semiconductor layer and (ii) a second signal metal layer stacked directly on the first signal metal layer so as to partially cover an upper surface of the first signal metal layer, wherein
- at the upper surface of the semiconductor layer, the first signal metal layer includes a first signal metal layer extended portion extending laterally toward a central portion of the channel layer, the first signal metal layer extended portion is exposed from the second signal metal layer and has a length between 0.4 μm and 1.5 μm, and
- the drain electrode includes (i) a first drain metal layer stacked directly on the semiconductor layer so as to partially cover an upper surface of the semiconductor layer and (ii) a second drain metal layer stacked directly on the first drain metal layer so as to partially cover an upper surface of the first drain metal layer, wherein
- at the upper surface of the semiconductor layer, the first drain metal layer includes a first drain metal layer extended portion extending laterally towards the central portion of the channel layer, the first drain metal layer extended portion is exposed from the second drain metal layer and has a length between 0.4 μm and 1.5 μm.
Dependencies are inferred from the claim text.