Vertical structure non-volatile memory device having insulating regions that are formed as air gaps between selection transistors of adjacent memory cell strings

A vertical structure non-volatile memory device comprising:

• a plurality of semiconductor regions vertically extending on a substrate;
• memory cell strings vertically extending on the substrate, each of the memory cell strings comprising a plurality of memory cells and at least one pair of first selection transistors;
• a plurality of connection electrodes, vertically extending on the substrate, each connected to at least one of the pairs of first selection transistors such that gate electrodes of the at least one pair of first selection transistors in a same one of the memory cell strings are connected to each other;
• a first selection line commonly connected to the gate electrodes of the at least one pair of first selection transistors through a first connection electrode among the plurality of connection electrodes;
• and
• a plurality of air gaps between adjacent ones of the memory cell strings, wherein a width of at least one of the plurality of air gaps is defined by the plurality of connection electrodes,
• wherein a height of the at least one air gap is higher than a height of any of the plurality of the connection electrodes, and
• wherein upper ends of the plurality of connection electrodes protrude above interlayer insulating layers adjacent the gate electrodes.

A vertical structure non-volatile memory device comprising:

• semiconductor regions vertically extending on a substrate;
• a first memory cell string vertically extending on the substrate and comprising a plurality of first memory cells and at least one first selection transistor, the plurality of first memory cells including a first gate electrode;
• a second memory cell string vertically extending on the substrate and comprising a plurality of second memory cells and at least one second selection transistor, the plurality of second memory cells including a second gate electrode connected to the first gate electrode;
• an interlayer insulating material on top surfaces of the at least one first selection transistor and the at least one second selection transistor;
• a first connection electrode that covers a sidewall of the at least one first selection transistor and a sidewall of the interlayer insulating material;
• a second connection electrode covers a sidewall of the at least one second selection transistor and another sidewall of the interlayer insulating material;
• bitlines connected to ends of the first and second memory cell strings;
• a first air gap between the at least one first selection transistor and the at least one second selection transistor and being spaced apart from the substrate by a distance greater than a height of at least one of the first gate electrode and the second gate electrode;
• and
• a length and a height of the first or second connection electrodes, and a distance between the first and second connection electrodes define a shape of the first air gap,
• wherein the first air gap extends in a direction crossing longitudinal directions of the bitlines, the first memory cell string, and the second memory cell string.