Integrated circuit with integrated decoupling capacitors

An integrated circuit formed at a semiconducting surface of a substrate, comprising:

• a plurality of non-volatile memory cells, each memory cell comprising a memory cell capacitor having a capacitor dielectric formed of a ferroelectric material;
• first and second ferroelectric capacitors, each having a capacitor dielectric formed of the ferroelectric material, disposed between first and second plates, wherein the second plate of the first ferroelectric capacitor is connected to the first plate of the second ferroelectric capacitor, so that the first and second ferroelectric capacitors are connected in series with one another between a first node coupled to the first plate of the first ferroelectric capacitor and a second node coupled to the second plate of the second ferroelectric capacitor;
• and
• a poly-to-active capacitor comprising:
• an active region at the semiconducting surface, the active region having a conductivity type opposite from that of the substrate, and having portions underlying the first and second ferroelectric capacitors;
• and
• a contiguous polycrystalline silicon plate having portions underlying the first and second ferroelectric capacitors, the polycrystalline silicon plate overlying the active region and separated there from by a capacitor dielectric layer.