Stack packages having token ring loops

A stack package comprising:

• a substrate having a first bond finger, a second bond finger and a third bond finger;
• a first semiconductor chip group including a plurality first semiconductor chips stacked on the substrate and a second semiconductor chip group including a plurality of second semiconductor chips stacked on the first semiconductor chip group, each of the first semiconductor chips and the second semiconductor chips having an input bonding pad, an output bonding pad and a dummy pad;
• a first token ring loop including a first interconnection electrically connect the first bond finger of the substrate to the input bonding pad of a lowermost first semiconductor chip of the first semiconductor chips, a second interconnection to electrically connect the output bonding pad of a lower first semiconductor chip of the first semiconductor chips to the input bonding pad of an upper first semiconductor chip stacked on the lower first semiconductor chip, a third interconnection to electrically connect the output bonding pad of an upper first semiconductor chip of the first semiconductor chips to the dummy pad of a lower first semiconductor chip under the upper first semiconductor chip, and a fourth interconnection to electrically connect the dummy pad of a lowermost first semiconductor chip of the first semiconductor chips to the second bond finger of the substrate;
• and
• a second token ring loop including a first interconnection to electrically connect the second bond finger of the substrate to the input bonding pad of a lowermost second semiconductor chip of the second semiconductor chips, a second interconnection to electrically connect the output bonding pad of a lower second semiconductor chip of the second semiconductor chips to the input bonding pad of an upper second semiconductor chip stacked on the lower second semiconductor chip, a third interconnection to electrically connect the output bonding pad of an upper second semiconductor chip of the second semiconductor chips to the dummy pad of a lower second semiconductor chip under the upper second semiconductor chip, and a fourth interconnection to electrically connect the dummy pad of a lowermost second semiconductor chip of the second semiconductor chips to the third bond finger of the substrate.