Semiconductor memory devices and semiconductor packages
AssigneeSamsung Electronics Co., Ltd.
InventorsHo-Cheol Lee, Chi-Sung Oh, Jin-Kuk Kim
Life of this patent
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Abstract
A semiconductor memory device includes a semiconductor die and an input-output bump pad part. The semiconductor die includes a plurality of memory cell arrays. The input-output bump pad part is formed in a central region of the semiconductor die. The input-output bump pad part provides a plurality of channels for connecting each of the memory cell arrays independently to an external device. The semiconductor memory device may adopt the multi-channel interface, thereby having high performance with relatively low power consumption.
Claims20
A semiconductor memory device comprising:
- a plurality of semiconductor dies that are stacked, each semiconductor die including a plurality of memory cell arrays;
- and
- a plurality of input-output bump pad parts respectively located at a central region of each semiconductor die, the input-output bump pad parts providing a plurality of channels each dedicated to only a respective one of the memory cell arrays and by which each of the memory cell arrays can be connected independently of each other to one or more external devices,
- wherein each of the input-output bump pad parts includes a plurality of channel bump pad parts associated with the memory cell arrays, respectively,
- each of the channel bump pad parts includes a plurality of bump pads that are arranged in a matrix of rows and columns, and
- the bump pads of each of the channel bump parts include power bump pads dedicated to receive power supply voltages.
A semiconductor memory device comprising:
- a plurality of semiconductor dies that are stacked, each semiconductor die including a plurality of memory cell arrays;
- a plurality of input-output bump pad parts respectively located at a central region of each semiconductor die, the input-output bump pad parts providing a plurality of channels each dedicated to only a respective one of the memory cell arrays and by which each of the memory cell arrays can be connected independently of each other to one or more external devices;
- and
- a plurality of test pad parts respectively located at each semiconductor die for testing operations of the semiconductor memory device.
A semiconductor package comprising:
- a base substrate;
- a controller chip disposed on the base substrate;
- and
- at least one semiconductor memory device disposed on the controller chip, the semiconductor memory device comprising:
- a semiconductor die including,
- a plurality of memory cell arrays;
- and
- an input-output bump pad part located at a central region of the semiconductor die, the input-output bump pad part providing a plurality of channels each dedicated to only a respective one of the memory cell arrays and by which each of the memory cell arrays can be connected independently of each other to the controller chip,
- wherein each of the input-output bump pad parts includes a plurality of channel bump pad parts associated with the memory cell arrays, respectively,
- each of the channel bump pad parts includes a plurality of bump pads that are arranged in a matrix of rows and columns, and
- the bump pads of each of the channel bump parts include power bump pads dedicated to receive power supply voltages.
Dependencies are inferred from the claim text.