Adaptive standard cell architecture and layout techniques for low area digital SoC

A method of operating a standard cell complementary metal oxide semiconductor (CMOS) device, comprising:

• providing power to a set of CMOS transistor devices through a first power rail and a second power rail, the first power rail extending across the standard cell, the first power rail being connected to one of a first voltage or a second voltage less than the first voltage, the second power rail extending across the standard cell, the second power rail being connected to an other one of the first voltage or the second voltage, the second power rail including a metal x layer interconnect and a set of metal x−1 layer interconnects connected to the metal x layer interconnect, the set of CMOS transistor devices being between the first power rail and the second power rail;
• and
• flowing a current through an x−1 layer interconnect extending under the second power rail and orthogonal to the second power rail, the x−1 layer interconnect being coupled to the set of CMOS transistor devices.

A standard cell complementary metal oxide semiconductor (CMOS) device apparatus, comprising:

• means for providing power to a set of CMOS transistor devices through a first power rail and a second power rail, the first power rail extending across the standard cell, the first power rail being connected to one of a first voltage or a second voltage less than the first voltage, the second power rail extending across the standard cell, the second power rail being connected to an other one of the first voltage or the second voltage, the second power rail including a metal x layer interconnect and a set of metal x−1 layer interconnects connected to the metal x layer interconnect, the set of CMOS transistor devices being between the first power rail and the second power rail;
• and
• means for flowing a current through an x−1 layer interconnect extending under the second power rail and orthogonal to the second power rail, the x−1 layer interconnect being coupled to the set of CMOS transistor devices.