US 9,070,551 B2Granted

Method and apparatus for a diffusion bridged cell library

AssigneeQUALCOMM Incorporated

InventorsBenjamin John Bowers, James W. Hayward, Charanya Gopal, Gregory Christopher Burda, Robert J. Bucki, Chock H. Gan, Giridhar Nallapati, Matthew D. Youngblood, William R. Flederbach

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Abstract

A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.

Claims7

Dependent claims

An apparatus comprising an integrated circuit, the integrated circuit comprising:

a supply rail;
a ground rail;
and
a first cell, the first cell having a left edge and a right edge, the first cell comprising:
a p-doped diffusion region contained in the first cell and continuous from the left edge to the right edge, the p-doped diffusion region electrically connected to the supply rail;
a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the supply rail;
an n-doped diffusion region contained in the first cell and continuous from the left edge to the right edge, the n-doped diffusion region electrically connected to the ground rail;
a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the ground rail;
a left floating polysilicon gate disposed over the p-doped diffusion region and n-doped diffusion region and proximal to the left edge;
and
a right floating polysilicon gate disposed over the p-doped diffusion region and n-doped diffusion region and proximal to the right edge.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/974,135Filed 23 Aug 2013 · us provisional application
Priority: 18 Jun 2013
Published: US 2014/0367760 A118 Dec 2014
Granted: 30 Jun 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
G06F 30/39
Circuit design: circuit design at the physical level
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…