Multi-chip package semiconductor memory device

A semiconductor memory device comprising:

• a plurality of memory chips;
• a memory controller chip that designates an address of one of said memory chips according to an access request received from outside and controls access to the designated address;
• a common bus configured to transmit signals between the memory controller chip and the memory chips;
• and
• dedicated buses separated from said common bus and provided for each of the memory chips and configured to transmit signals between said memory controller chip and said memory chips,
• wherein each of the memory chips includes first and second storage regions, and an information holder that holds address information representing an association between a specific address corresponding to a defective cell in the first storage region and an address in the second storage region, and
• the memory controller chip includes an address translating part that performs, upon receiving a request to access the specific address in the first storage region indicated by the address information, address designation by translating the specific address in the first storage region to an address in the second storage region corresponding to the specific address based on the association represented by the address information,
• wherein said address information represents an association between an address of a defective cell in the first storage region and an address of a memory cell in the second storage region,
• the memory controller chip includes a table holder that holds a table including said address information,
• the address translating part performs address translation based on said address information included in the table, wherein said memory controller chip includes a plurality of table holders which are provided respectively in association with said plurality of memory chips, and the address information in each of the plurality of table holders represents an association between an address of a defective cell in the first storage region and an address of a memory cell in the second storage region in each of the plurality of memory chips, and
• wherein said memory control chip designates a translated address in the second storage region via the dedicated bus in accordance with a request to access the address of the defective cell in the first storage region, and designates a requested address in the first storage region via the common bus in accordance with a request to access the address of the non-defective cell in the first storage region.