Semiconductor memory device and memory system including the same
AssigneeSK hynix Inc.
InventorSang Oh Lim
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device includes a first memory unit and a plurality of second memory unit, each including a plurality of memory cells and page buffers corresponding to the memory cells, and a redundancy memory unit including a plurality of redundancy memory cells and a plurality of redundancy page buffers corresponding to the redundancy memory cells. First input/output (I/O) data lines coupled to the first memory unit and second I/O data lines coupled to the second memory unit are coupled to the redundancy memory unit.
Claims19
A semiconductor memory device comprising:
- a first memory unit and a second memory unit, each including a plurality of memory cells and a plurality of page buffers corresponding to the memory cells;
- and
- a redundancy memory unit including a plurality of redundancy memory cells and a plurality of redundancy page buffers corresponding to the redundancy memory cells,
- wherein first input/output (I/O) data lines coupled to the first memory unit and second I/O data lines coupled to the second memory unit are coupled to the redundancy memory unit,
- wherein, when memory cells having the same address in the first and second memory units are determined as defective cells, different redundancy column selection signals are assigned by coding addresses corresponding to the first memory unit and the second memory unit, respectively.
A semiconductor memory device comprising:
- a low-byte main memory unit and a high-byte main memory unit, each including a plurality of memory cells and a plurality of page buffers corresponding to the memory cells;
- and
- a redundancy memory unit including a plurality of redundancy memory cells and a plurality of redundancy page buffers corresponding to redundancy memory cells,
- wherein the low-byte main memory unit and the high-byte main memory unit share the redundancy memory unit with each other during a redundancy operation,
- wherein, when memory cells having the same address in the low-byte main memory unit and the high-byte main memory unit are determined as defective cells, different redundancy column selection signals are assigned by coding addresses corresponding to the high-byte main memory unit and the low-byte main memory unit, respectively.
A memory system comprising:
- a semiconductor memory device including a first memory unit, a second memory unit, and a redundancy memory unit suitable for performing a redundancy operation on the first and second memory units;
- and
- a controller suitable for controlling the semiconductor memory device,
- wherein the first memory unit and the second memory unit share the redundancy memory unit with each other during the redundancy operation,
- wherein, when memory cells having the same address in the first memory unit and the second memory unit are determined as defective cells, different redundancy column selection signals are assigned by coding addresses corresponding to the first memory unit and the second memory unit, respectively.
Dependencies are inferred from the claim text.