Bit interleaved low voltage static random access memory (SRAM) and related methods
AssigneeMie Fujitsu Semiconductor Limited
InventorLawrence T. Clark
Life of this patent
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Abstract
A method can include applying a device power supply voltage to an integrated circuit including a static random access memory (SRAM) with transistors having at least a first threshold voltage (Vt); applying an array power supply voltage to cells of the SRAM that is near or below Vt; and in a write operation, reading data from at least a first group of the cells that is interleaved with a second group of the cells, and applying the read data to the bit lines of the first group of cells, while write data is applied to the bit lines of the second group of cells.
Claims20
A method, comprising:
- applying a device power supply voltage to an integrated circuit including a static random access memory (SRAM) with transistors having at least a first threshold voltage (Vt);
- applying an array power supply voltage to cells of the SRAM that is near or below Vt;
- and
- in a write operation,
- reading data from at least a first group of the cells that is interleaved with a second group of the cells, and
- applying the read data to the bit lines of the first group of cells, while write data is applied to the bit lines of the second group of cells.
An integrated circuit, comprising:
- at least one static random access memory (SRAM) comprising cells arranged into interleaved groups configured to receive an array power supply voltage;
- and
- write circuits configured to apply data read from one of the interleaved groups to bit lines of the interleaved group and while write data is applied to bit lines of the other of the interleaved groups;
- wherein
- the cells comprise transistors having at least a first threshold voltage (Vt), and the array power supply voltage is near or below Vt.
An integrated circuit, comprising:
- a plurality of static random access memory (SRAM) cells arranged into interleaved groups, the plurality of SRAM cells comprising columns, the plurality of SRAM cells coupled to receive an array power supply voltage, each SRAM cell including
- a latch circuit coupled to at least one write bit line by a first access device coupled to a write word line, the latch circuits comprising transistors having at least a first threshold voltage (Vt), and
- a read circuit configured to establish a voltage on a read bit line in response to activation of a corresponding read word line;
- write circuits configured to apply data read from one of the interleaved groups to write bit lines of the interleaved group while applying write data to write bit lines of the other of the interleaved groups;
- wherein
- the array power supply voltage is near or below Vt.
Dependencies are inferred from the claim text.