Reading soft bits simultaneously

A non-volatile storage device comprising:

• a plurality of NAND strings of non-volatile storage elements, the NAND strings include a first NAND string having a first non-volatile storage element and a second NAND string having a second non-volatile storage element;
• a plurality of word lines associated with the plurality of NAND strings;
• and
• one or more managing circuits in communication with the non-volatile storage elements, the one or more managing circuits are configured to program the non-volatile storage elements to “n+1” data states, each data state corresponding to a range of threshold voltages, the one or more managing circuits are configured to perform “n” sense operations at “n” references voltages to determine whether the threshold voltage of each non-volatile storage element in a subset of the non-volatile storage elements is greater or less than each of the “n” references voltages, the one or more managing circuits are configured to perform an additional sense operation for each of the “n” sense operations, including the one or more managing circuits being configured to simultaneously sense a first group of non-volatile storage elements in the subset that have a threshold voltage greater than the “nth” reference voltage at a first offset voltage from the “nth” reference voltage while sensing a second group of non-volatile storage elements in the subset that have a threshold voltage less than the “nth” reference voltage at a second offset voltage from the “nth” reference voltage, the first offset is different from the second offset.

A non-volatile storage device comprising:

• a plurality of NAND strings of non-volatile storage elements, the NAND strings include a first NAND string having a first non-volatile storage element and a second NAND string having a second non-volatile storage element;
• a plurality of word lines associated with the plurality of NAND strings;
• and
• managing circuitry in communication with the non-volatile storage elements, the managing circuitry is configured to program the non-volatile storage elements to “n+1” data states, the managing circuitry is configured to perform “n” sense operations at “n” references voltages to determine which of n+1 adjacent voltage bands each non-volatile storage element is in, the managing circuitry is configured to perform an additional sense operation for each of the “n” sense operations, the additional sense operations are performed near edges of the voltage bands, including the managing circuitry being configured to simultaneously sense a first group of the non-volatile storage elements that have a threshold voltage just above the respective voltage band edge and a second group of the non-volatile storage elements that have a threshold voltage just below the respective voltage band edge.

A non-volatile storage device comprising:

• a three-dimensional memory array, the three-dimensional memory array comprising a plurality of NAND strings of non-volatile storage elements;
• a plurality of word lines associated with the plurality of NAND strings;
• and
• managing circuitry in communication with the non-volatile storage elements, the managing circuitry is configured to program the non-volatile storage elements to “n+1” data states, the managing circuitry is configured to perform “n” sense operations at “n” references voltages to determine which of n+1 adjacent voltage bands each non-volatile storage element is in, the managing circuitry is configured to perform an additional sense operation for each of the “n” sense operations, the additional sense operations are performed near edges of the voltage bands to read soft bits, including the managing circuitry being configured to simultaneously sense a first group of the non-volatile storage elements that have a threshold voltage just above the respective voltage band edge and a second group of the non-volatile storage elements that have a threshold voltage just below the respective voltage band edge.