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US 9,070,473 B2Granted
Refresh architecture and algorithm for non-volatile memories
AssigneeMicron Technology, Inc.
InventorsFerdinando Bedeschi, Roberto Gastaldi
Life of this patent
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Abstract
Methods and systems to refresh a non-volatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.
Claims18
A method of refreshing a memory cell array in a non-volatile memory device, the method comprising:
- performing a first refresh and second refresh as a function of a system state identifier,
- wherein performing the first refresh further comprises:
- reading cells of the memory array against a first refresh reference level and reprogramming those cells which fail;
- and
- wherein the performance of the second refresh further comprises:
- reading cells of the memory array against a second refresh reference level that is different than the first refresh reference level and reprogramming those cells which store data corrected by an error correction encoding algorithm;
- reading data from a first subset of memory cells;
- applying the error correction algorithm to the data read from the first subset of memory cells;
- writing the error corrected data into a volatile cache memory;
- and
- wherein the programming comprises copying the error corrected data from the cache memory back into the first subset of memory cells.
8 more elements
A non-volatile memory device, comprising:
- an array of memory cells;
- a refresh controller configured to perform a first refresh and second refresh as a function of a system state identifier, wherein performing the first refresh further comprises:
- reading cells of the memory array against a first refresh reference level and reprogramming those cells which fail;
- wherein the performance of the second refresh further comprises:
- reading cells of the memory array against a second refresh reference level that is different than the first refresh reference level and reprogramming those cells which store data corrected by an error correction encoding algorithm;
- a cache memory to store data from a first subset of the memory cells read out in response to the refresh controller initiating the second refresh;
- an error correction encoding module to error correct the data read from the first subset of memory cells;
- a flag bit register to store a flag value in response to an error correction of the data read from the subset of memory cells;
- and
- a multiplexer coupled to the cache memory and the memory array to copy the error corrected data from the cache memory back to the first subset of memory cells in response to the flag value.
7 more elements
A system, comprising:
- a memory controller unit;
- a non-volatile memory device coupled to the memory controller unit, wherein
- the memory device is configured to perform a first refresh and second refresh as a function of the system state identifier, wherein performing the first refresh further comprises:
- reading cells of the memory array against a first refresh reference level and reprogramming those cells which fail;
- wherein the performance of the second refresh further comprises:
- reading cells of the memory array against a second refresh reference level that is different than the first refresh reference level and reprogramming those cells which store data corrected by an error correction encoding algorithm;
- a cache memory to store data from a first subset of the memory cells read out in response to the refresh controller initiating the second refresh;
- an error correction encoding module to error correct the data read from the first subset of memory cells;
- a flag bit register to store a flag value in response to an error correction of the data read from the subset of memory cells;
- and
- a multiplexer coupled to the cache memory and the memory array to copy the error corrected data from the cache memory back to the first subset of memory cells in response to the flag value.
8 more elements
Dependencies are inferred from the claim text.