Shift register, display-driving circuit, displaying panel, and displaying device

A shift register for use in a display-driving circuit which carries out simultaneous selection of a plurality of signal lines at a timing, the shift register comprising:

• a stage, the stage including,
• a set-reset type flip-flop, and
• a signal generating circuit configured to receive a simultaneous selection signal, the signal generating circuit configured to generate an output signal of the stage based on an output of the flip-flop wherein,
• the output signal of the stage (i) becomes active due to an activation of the simultaneous selection signal and then (ii) remains active during the simultaneous selection,
• the output of the flip-flop (a) is active during a set period in which a setting signal is active, and (b) is inactive during a reset period in which a resetting signal is active,
• the flip-flop is configured to cause the resetting signal to have priority over the setting signal such that the output of the flip-flop is a same state as the reset period while (i) the setting signal has the same state as the set period, and (ii) the resetting signal has the same state as the reset period,
• the flip-flop is configured to (1) receive as the setting signal one of an output signal from a preceding stage, and an inverted version of the output signal from the preceding stage, and (2) receive as the resetting signal one of the output signal of the stage, an inverted version of the output signal of the stage, an output signal from a successive stage, and an inverted version of the output signal from the successive stage, and
• the output of the flip-flop is the same state as the reset period during the simultaneous selection.