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US 9,070,459 B2Granted
Erase operation control sequencing apparatus, systems, and methods
AssigneeMicron Technology, Inc.
InventorsXiaojun Yu, Jin-man Han, Aaron Yip
Life of this patent
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Abstract
Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
Claims24
An apparatus, comprising:
- an erase initiation circuit coupled to an erasable memory array, and configured to apply a global select gate voltage to wordline transistors coupled to the erasable memory array during an erase operation after an initiation voltage has reached a preselected value that is less than an ultimate erase voltage, wherein select gates of the wordline transistors are grounded at an initial stage of the erase operation, and wherein the erasable memory array comprises a plurality of floating gate transistors.
An apparatus, comprising:
- an erase initiation circuit coupled to an erasable memory array, and configured to apply a global select gate voltage to a plurality of wordline transistors of the erasable memory array during an erase operation after an initiation voltage has reached a preselected initiation level that is less than an ultimate erase voltage, wherein select gates of the wordline transistors are grounded at an initial stage of the erase operation;
- and
- a control circuit coupled to the erasable memory array and configured to receive an external erase command, the control circuit having a voltage detection circuit to detect the initiation voltage.
A method, comprising:
- applying a global select gate voltage to wordline transistors coupled to an erasable memory array, during an erase operation after an initiation voltage has reached a preselected initiation level that is less than an ultimate erase voltage, wherein select gates of the wordline transistors are grounded at an initial stage of the erase operation.
An apparatus, comprising:
- an erase initiation circuit configured to allow a select gate conductor of a wordline transistor of a memory array to rise to a first voltage during an erase operation only after an initiation voltage has reached an initiation level between a reference voltage and an ultimate erase voltage, wherein the select gate conductor is grounded at an initial stage of the erase operation.
Dependencies are inferred from the claim text.