US 9,070,453 B2Granted

Multiple programming of flash memory without erase

AssigneeRamot at Tel-Aviv University Ltd.

InventorsEran Sharon, Idan Alrod, Simon Litsyn, Ishai Ilani

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Abstract

To store, successively, in a plurality of memory cells, first and second pluralities of input bits that are equal in number, a first transformation transforms the first input bits into a first plurality of transformed bits. A first portion of the cells is programmed to store the first transformed bits according to a mapping of bit sequences to cell levels, but, if the first transformation has a variable output length, only if there are few enough first transformed bits to fit in the first cell portion. Then, without erasing a second cell portion that includes the first portion, if respective levels of the cells of the second portion, that represent a second plurality of transformed bits obtained by a second transformation of the second input bits, according to the mapping, are accessible from the current cell levels, the second portion is so programmed to store the second transformed bits.

Claims39

Dependent claims

A method of attempting to store, successively, in a plurality of memory cells, a first plurality of input bits and a second plurality of input bits, comprising:

(a) providing a mapping of bit sequences to cell levels of the memory cells, wherein the cell levels for each memory cell comprise a lower level and an upper level with each lower level having a lower threshold voltage than the corresponding upper level;
(b) transforming the first plurality of input bits to a first plurality of transformed bits, using a first transformation, wherein the first transformation is biased downwards towards the lower half of the cell levels such that programming the transformed bits according to the mapping would result in more memory cells being programmed to the lower half of the cell levels than to the upper half of the cell levels;
(c) programming at least a first portion of the memory cells to store the first plurality of transformed bits according to the mapping;
and
(d) subsequent to the programming of the at least first portion of the memory cells, and without erasing at least a second portion of the memory cells that includes the at least first portion of the memory cells:
(i) determining, for the at least second portion of the memory cells, whether respective levels, of the at least second portion of the memory cells, that represent, according to the mapping, a second plurality of transformed bits obtained by transforming the second plurality of input bits using a second transformation, are accessible from the current respective cell levels of the at least second portion of the memory cells, wherein the second plurality of transformed bits are a representation of a codeword selected from a plurality of codeword representations of the second plurality of input bits generated using the second transformation, and
(ii) only if the respective levels, of the at least second portion of the memory cells, that represent, according to the mapping, the second plurality of transformed bits obtained by transforming the second plurality of input bits using the second transformation, are accessible from the current respective cell levels of the at least second portion of the memory cells:
programming the at least second portion of the memory cells to store the second plurality of transformed bits according to the mapping.

5 more elements

A memory device comprising:

(a) a plurality of memory cells;
and
(b) a controller operative to attempt to store, successively, in the plurality of memory cells, a first plurality of input bits and a second plurality of input bits, by:
(i) transforming the first plurality of input bits to a first plurality of transformed bits, using a first transformation,
(ii) programming at least a first portion of the memory cells to store the first plurality of transformed bits according to a mapping of bit sequences to cell levels of the memory cells, wherein the cell levels for each memory cell comprise a lower level and an upper level with each lower level having a lower threshold voltage than the corresponding upper level and wherein the first transformation is biased downwards towards the lower half of the cell levels such that programming the transformed bits according to the mapping would result in more memory cells being programmed to the lower half of the cell levels than to the upper half of the cell levels, and
(iii) subsequent to the programming of the at least first portion of the memory cells, and without erasing at least a second portion of the memory cells that includes the at least first portion of the memory cells:
(A) determining, for the at least second portion of the memory cells, whether respective levels, of the at least second portion of the memory cells, that represent, according to the mapping, a second plurality of transformed bits obtained by transforming the second plurality of input bits using a second transformation, are accessible from the current respective cell levels of the at least second portion of the memory cells, wherein the second plurality of transformed bits are a representation of a codeword selected from a plurality of codeword representations of the second plurality of input bits generated using the second transformation, and
(B) only if the respective levels, of the at least second portion of the memory cells, that represent, according to the mapping, the second plurality of transformed bits obtained by transforming the second plurality of input bits using the second transformation, are accessible from the current respective cell levels of the at least second portion of the memory cells:
programming the at least second portion of the memory cells to store the second plurality of transformed bits according to the mapping.

6 more elements

A system for storing input bits, comprising:

(a) a memory device that includes a plurality of memory cells;
and
(b) a processor operative to attempt to store, successively, in the plurality of memory cells, a first plurality of the input bits and a second plurality of the input bits, by:
(i) transforming the first plurality of the input bits to a first plurality of transformed bits, using a first transformation,
(ii) programming at least a first portion of the memory cells to store the first plurality of transformed bits according to a mapping of bit sequences to cell levels of the memory cells, wherein the cell levels for each memory cell comprise a lower level and an upper level with each lower level having a lower threshold voltage than the corresponding upper level and wherein the first transformation is biased downwards towards the lower half of the cell levels such that programming the transformed bits according to the mapping would result in more memory cells being programmed to the lower half of the cell levels than to the upper half of the cell levels, and
(iii) subsequent to the programming of the at least first portion of the memory cells, and without erasing at least a second portion of the memory cells that includes the at least first portion of the memory cells:
(A) determining, for the at least second portion of the memory cells, whether respective levels, of the at least second portion of the memory cells, that represent, according to the mapping, a second plurality of transformed bits obtained by transforming the second plurality of the input bits using a second transformation, are accessible from the current respective cell levels of the at least second portion of the memory cells, wherein the second plurality of transformed bits are a representation of a codeword selected from a plurality of codeword representations of the second plurality of input bits generated using the second transformation, and
(B) only if the respective levels, of the at least second portion of the memory cells, that represent, according to the mapping, the second plurality of transformed bits obtained by transforming the second plurality of the input bits using the second transformation, are accessible from the current respective cell levels of the at least second portion of the memory cells:
programming the at least second portion of the memory cells to store the second plurality of transformed bits according to the mapping.

6 more elements

A non-transitory computer-readable storage medium having computer-readable code embodied in the computer-readable storage medium, the computer-readable code for storing input bits in a plurality of memory cells, the computer-readable code comprising program code for attempting to store, successively, in the plurality of memory cells, a first plurality of the input bits and a second plurality of the input bits, by:

(a) transforming the first plurality of the input bits to a first plurality of transformed bits, using a first transformation;
(b) programming at least a first portion of the memory cells to store the first plurality of transformed bits according to a mapping of bit sequences to cell levels of the memory cells, wherein the cell levels for each memory cell comprise a lower level and an upper level with each lower level having a lower threshold voltage than the corresponding upper level and wherein the first transformation is biased downwards towards the lower half of the cell levels such that programming the transformed bits according to the mapping would result in more memory cells being programmed to the lower half of the cell levels than to the upper half of the cell levels;
and
(c) subsequent to the programming of the at least the first portion of the memory cells, and without erasing at least a second portion of the memory cells that includes the at least the first portion of the memory cells:
(i) determining, for the at least second portion of the memory cells, whether respective levels, of the at least second portion of the memory cells, that represent, according to the mapping, a second plurality of transformed bits obtained by transforming the second plurality of the input bits using a second transformation, are accessible from the current respective cell levels of the at least second portion of the memory cells, wherein the second plurality of transformed bits are a representation of a codeword selected from a plurality of codeword representations of the second plurality of input bits generated using the second transformation, and
(ii) only if the respective levels, of the at least second portion of the memory cells, that represent, according to the mapping, the second plurality of transformed bits obtained by transforming the second plurality of the input bits using the second transformation, are accessible from the current respective cell levels of the at least second portion of the memory cells:
programming the at least second portion of the memory cells to store the second plurality of transformed bits according to the mapping.

4 more elements

A method of attempting to store, successively, in a plurality of memory cells, a first plurality of input bits and a second plurality of input bits, comprising:

(a) providing a mapping of bit sequences to cell levels of the memory cells, wherein the cell levels for each memory cell comprise a lower level and an upper level with each lower level having a lower threshold voltage than the corresponding upper level;
(b) transforming the first plurality of input bits to a first plurality of transformed bits, using a first transformation that has a variable output length, wherein the first transformation is biased downwards towards the lower half of the cell levels such that programming the transformed bits according to the mapping would result in more memory cells being programmed to the lower half of the cell levels than to the upper half of the cell levels;
(c) determining whether the first plurality of transformed bits is small in number such that at least a first portion of the memory cells are programmable to store the first plurality of transformed bits according to the mapping;
and
(d) only if the first plurality of transformed bits is small in number such that the at least first portion of the memory cells are programmable to store the first plurality of transformed bits according to the mapping:
(i) programming the at least first portion of the memory cells to store the first plurality of transformed bits according to the mapping,
(ii) transforming the second plurality of input bits to a second plurality of transformed bits, using a second transformation such that, for at least a second portion of the memory cells that includes the at least first portion of the memory cells, respective cell levels of the at least second portion of the memory cells that represent the second plurality of transformed bits according to the mapping are accessible from the current respective cell levels of the at least second portion of the memory cells, wherein the second plurality of transformed bits are a representation of a codeword selected from a plurality of codeword representations of the second plurality of input bits generated using the second transformation, and
(iii) programming the at least second portion of the memory cells to store the second plurality of transformed bits according to the mapping without erasing the at least second portion of the memory cells between the programming of the at least first portion of the memory cells to store the first plurality of transformed bits and the programming of the at least second portion of the memory cells to store the second plurality of transformed bits.

5 more elements

A memory device comprising:

(a) a plurality of memory cells;
and
(b) a controller operative to attempt to store, successively, in the plurality of memory cells, a first plurality of input bits and a second plurality of input bits, by:
(i) transforming the first plurality of input bits to a first plurality of transformed bits, using a first transformation that has a variable output length,
(ii) determining whether the first plurality of transformed bits is small in number such that at least a first portion of the memory cells are programmable to store the first plurality of transformed bits according to a mapping of bit sequences to cell levels of the memory cells, wherein the cell levels for each memory cell comprise a lower level and an upper level with each lower level having a lower threshold voltage than the corresponding upper level and wherein the first transformation is biased downwards towards the lower half of the cell levels such that programming the transformed bits according to the mapping would result in more memory cells being programmed to the lower half of the cell levels than to the upper half of the cell levels, and
(iii) only if the first plurality of transformed bits is small in number such that the at least first portion of the memory cells are programmable to store the first plurality of transformed bits according to the mapping:
(A) programming the at least first portion of the memory cells to store the first plurality of transformed bits according to the mapping,
(B) transforming the second plurality of input bits to a second plurality of transformed bits, using a second transformation such that, for at least a second portion of the memory cells that includes the first portion of the memory cells, respective cell levels of the at least second portion of transformed bits according to the mapping are accessible from the current respective levels of the at least second portion of the memory cells, wherein the second plurality of transformed bits are a representation of a codeword selected from a plurality of codeword representations of the second plurality of input bits generated using the second transformation, and
(C) programming the at least second portion of the memory cells to store the second plurality of transformed bits according to the mapping without erasing the at least second portion of the memory cells between the programming of the at least first portion of the memory cells to store the first plurality of transformed bits and the programming of the at least second portion of the memory cells to store the second plurality of transformed bits.

6 more elements

A system for storing input bits, comprising:

(a) a memory device that includes a plurality of memory cells;
and
(b) a processor operative to attempt to store, successively, in the plurality of memory cells, a first plurality of the input bits and a second plurality of the input bits, by:
(i) transforming the first plurality of the input bits to a first plurality of transformed bits, using a first transformation that has a variable output length,
(ii) determining whether the first plurality of transformed bits is small in number such that at least a first portion of the memory cells are programmable to store the first plurality of transformed bits according to a mapping of bit sequences to cell levels of the memory cells, wherein the cell levels for each memory cell comprise a lower level and an upper level with each lower level having a lower threshold voltage than the corresponding upper level and wherein the first transformation is biased downwards towards the lower half of the cell levels such that programming the transformed bits according to the mapping would result in more memory cells being programmed to the lower half of the cell levels than to the upper half of the cell levels, and
(iii) only if the first plurality of transformed bits is small in number such that the at least first portion of the memory cells are programmable to store the first plurality of transformed bits according to the mapping:
(A) programming the at least first portion of the memory cells to store the first plurality of transformed bits according to the mapping,
(B) transforming the second plurality of the input bits to a second plurality of transformed bits, using a second transformation such that, for at least a second portion of the memory cells that includes the first portion of the memory cells, respective cell levels of the at least second portion of transformed bits according to the mapping are accessible from the current respective levels of the at least second portion of the memory cells, wherein the second plurality of transformed bits are a representation of a codeword selected from a plurality of codeword representations of the second plurality of input bits generated using the second transformation, and
(C) programming the at least second portion of the memory cells to store the second plurality of transformed bits according to the mapping without erasing the at least second portion of the memory cells between the programming of the at least first portion of the memory cells to store the first plurality of transformed bits and the programming of the at least second portion of the memory cells to store the second plurality of transformed bits.

6 more elements

(a) transforming the first plurality of input bits to a first plurality of transformed bits, using a first transformation that has a variable output length;
(b) determining whether the first plurality of transformed bits is small in number such that at least a first portion of the memory cells are programmable to store the first plurality of transformed bits according to a mapping of bit sequences to cell levels of the memory cells, wherein the cell levels for each memory cell comprise a lower level and an upper level with each lower level having a lower threshold voltage than the corresponding upper level and wherein the first transformation is biased downwards towards the lower half of the cell levels such that programming the transformed bits according to the mapping would result in more memory cells being programmed to the lower half of the cell levels than to the upper half of the cell levels;
and
(c) only if the first plurality of transformed bits is small in number such that the at least first portion of the memory cells are programmable to store the first plurality of transformed bits according to the mapping:
(i) programming the at least first portion of the memory cells to store the first plurality of transformed bits according to the mapping,
(ii) transforming the second plurality of input bits to a second plurality of transformed bits, using a second transformation such that, for at least a second portion of the memory cells that includes the first portion of the memory cells, respective cell levels of the at least second portion of transformed bits according to the mapping are accessible from the current respective levels of the at least second portion of the memory cells, wherein the second plurality of transformed bits are a representation of a codeword selected from a plurality of codeword representations of the second plurality of input bits generated using the second transformation, and
(iii) programming the at least second portion of the memory cells to store the second plurality of transformed bits according to the mapping without erasing the at least second portion of the memory cells between the programming of the at least first portion of the memory cells to store the first plurality of transformed bits and the programming of the at least second portion of the memory cells to store the second plurality of transformed bits.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/086,408Filed 14 Apr 2011 · us provisional application
Priority: 15 Apr 2010
Published: US 2011/0258370 A120 Oct 2011
Granted: 30 Jun 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 16/102
Programming or data input circuits: external programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
G06F 12/02
Accessing, addressing or allocating within memory systems or architectures: addressing or allocation; Relocation
G11C 11/5628
Using charge storage in a floating gate: programming or writing circuits; Data input circuits
G11C 16/349
Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention: arrangements for evaluating…