Non-volatile multilevel memory cells
AssigneeMicron Technology, Inc.
InventorSeiichi Aritome
Life of this patent
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Abstract
The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a second cell coupled to the row select line, a second number of program states to which the second cell can be programmed, wherein the second number of program states is greater than the first number of program states. The method includes programming the first cell to one of the first number of program states prior to programming the second cell to one of the second number of program states.
Claims20
An apparatus, comprising:
- an array of memory cells;
- and
- a controller configured to:
- cause a first subset of commonly coupled memory cells to be programmed to one of a first number (E) of program states;
- cause a second subset of the commonly coupled memory cells to be programmed to one of a second number (O) of program states, wherein O is greater than E;
- and
- cause a third subset of the commonly coupled memory cells to be programmed to one of a third number (E2) of program states;
- wherein the first number of program states and/or the third number of program states corresponds to a respective non-integer number of bits.
An apparatus, comprising:
- an array of memory cells;
- and
- a controller configured to:
- cause a first subset of commonly coupled memory cells to be programmed to one of a first number (E) of program states;
- and
- cause a second subset of the commonly coupled memory cells to be programmed to one of a second number (O) of program states, wherein O is twice E;
- wherein the first number of program states and/or the second number of program states correspond to a respective non-integer number of bits.
An apparatus, comprising:
- an array of memory cells;
- and
- a controller configured to:
- cause a first subset of commonly coupled memory cells to be programmed to one of a first number (E) of program states;
- and
- cause a second subset of the commonly coupled memory cells to be programmed to one of a second number (O) of program states, wherein O is greater than E;
- wherein the first number of program states and/or the second number of program states correspond to a respective non-integer number of bits;
- wherein a first read margin is associated with the first subset of cells;
- and
- wherein a different read margin is associated with the second subset of cells.
Dependencies are inferred from the claim text.