Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsNaofumi Abiko, Masahiro Yoshihara, Akio Sugahara, Yoshikazu Harada
Life of this patent
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Abstract
A semiconductor memory device includes a memory cell array including memory cells arranged therein. A first latch circuit temporarily holds data to perform a read operation and a write operation on the memory cell array. The second latch circuit temporarily holds a control signal. A control circuit controls the memory cell array, the first latch circuit and the second latch circuit. The control circuit limits an operation of the first latch circuit in a state after an operation on the memory cell array has been finished, and limits an operation of the second latch circuit based on a command supplied from external.
Claims18
A semiconductor memory device, comprising:
- a memory cell array including memory cells;
- a first latch circuit operative to temporarily hold data;
- a second latch circuit operative to temporarily hold a control signal;
- and
- a control circuit configured to execute a first operation, the first operation including a write operation or a read operation,
- the control circuit being operative to stop an operation of the first latch circuit without stopping an operation of the second latch circuit after the first operation has been finished, and stop an operation of the second latch circuit when the semiconductor memory device receives a first command from external to the semiconductor memory device.
A semiconductor memory device comprising a memory chip and a memory controller operative to control the memory chip, the memory chip comprising:
- a memory cell array including memory cells;
- a first latch circuit operative to hold data;
- a second latch circuit operative to temporally hold a control signal;
- and
- a control circuit operative to execute a first operation, the first operation including a write operation or a read operation,
- the control circuit being operative to stop an operation of the first latch circuit after the first operation has been finished, and stop an operation of the second latch circuit when the semiconductor memory device receives a first command from the memory controller.
Dependencies are inferred from the claim text.