Non-volatile memory system with reset verification mechanism and method of operation thereof

A method of operation of a non-volatile memory system comprising:

• providing a resistive storage element having a high resistance state and a low resistance state including forming conductive threads in the low resistance state;
• coupling an analog multiplexer to the resistive storage element for applying a bias voltage including coupling a bit line and control bus for applying the bias voltage;
• and
• switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state including asserting a well switch for referencing the bias voltage to a well voltage when activating a read reference generator for establishing the verification bias to be ten times the voltage of the read bias.

A non-volatile memory system comprising:

• a resistive storage element having a high resistance state and a low resistance state;
• an analog multiplexer, coupled to the resistive storage element, for applying a bias voltage;
• and
• a read reference generator provides a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state includes a well switch coupled between a well voltage and the read reference generator for referencing the bias voltage to a well voltage.