Semiconductor device

A semiconductor device with a memory cell array, comprising:

• a booster circuit, the booster circuit comprising one or more booster units, each booster unit connected to a plurality of transistors, each transistor connected to a booster circuit output terminal, the booster units comprising:
• a first set of capacitors, a first member of the first set of capacitors having a first end supplied with a supply voltage and a second end supplied with a first clock signal,
• a first set of transistors including first and second transistors, the gate and drain of each first set transistor electrically connected to the first end of a corresponding member of the first set of capacitors, with each transistor of the first set connected in series as diodes with the drain and gate of a first member of the first set of transistors connected to the supply voltage, and the source of a last member of the first set of transistors connected to a booster unit output terminal,
• a second set of capacitors, a first member of the second set of capacitors having a first end supplied with the supply voltage and a second end supplied with a second clock signal, the second clock signal complementary to the first clock signal, and
• a second set of transistors including third and fourth transistors, the gate and drain of each second set transistor electrically connected to the first end of a corresponding member of the second set of capacitors, with each transistor of the second set connected in series as diodes with the drain and gate of a first member of the second set of transistors connected to the supply voltage, and the source of a last member of the second set of transistors connected to the booster unit output terminal,
• each of the first and second sets of capacitors of the booster unit formed in a layer stacked configuration, wherein a plurality of conductive layers are stacked with insulating layers in a stair-stepped configuration above a substrate, such that at least one end of each conductive layer is not overlapped by the conductive layer directly above, and includes first and second conductive layers that are each a first distance away from the substrate, the first conductive layer electrically connected to a gate of the first transistor and the second conductive layer electrically connected to a gate of the second transistor, and third and fourth conductive layers that are each a second distance, greater than the first distance, away from the substrate, the third conductive layer electrically connected to a gate of the third transistor and the fourth conductive layer electrically connected to a gate of the fourth transistor;
• and
• an oscillator circuit, the oscillator circuit having an input terminal and an output terminal, the input terminal connected to a clock signal supplied by a control circuit, and the output terminal of the oscillator circuit connected to an input terminal of the booster circuit, the oscillator circuit comprising one or more oscillator units, each oscillator unit connected in series, the oscillator units each comprising:
• a resistor with a first and second end,
• a capacitor with a first and second end, and
• a first inverter with a first and second end, wherein the first end of the resistor is supplied with a third clock signal, the second end of the resistor is connected to the second end of the capacitor and the first end of the first inverter, the first end of the capacitor is connected to a ground voltage, and the second end of the first inverter outputs a fourth clock signal.