SRAM supply voltage global bitline precharge pulse

A precharge generation circuit to generate timing control for an SRAM circuit operating with dual power supplies, the circuit comprising:

• a programmable local clock buffer configured to generate a voltage signal and to receive power from a first voltage level;
• a level shifter connected to the programmable local clock buffer, the level shifter configured to shift the voltage signal higher and to receive power from both the first voltage level and a second voltage level;
• a delay clock chopper circuit connected to the level shifter, the delay clock chopper circuit configured to delay the voltage signal and to receive power from the second voltage level, the delay clock chopper circuit including a programmable pulse width variation circuit;
• and
• the programmable pulse width variation circuit configured to vary a pulse width of the voltage signal and to receive power from the second voltage level;
• wherein a global bitline of the SRAM circuit is driven with the voltage signal, the voltage signal having timing sensitive to both the first voltage level and the second voltage level and the pulse width sensitive to the second voltage level.