Negative bitline boost scheme for SRAM write-assist
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-jer Hsieh, Yangsyu Lin, Hsiao Wen Lu, Chiting Cheng, Jonathan Tsung-Yung Chang
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Abstract
A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element.
Claims21
A device comprising:
- a transistor switch coupled between a bit line voltage node and a ground node;
- a boost signal circuit coupled to a gate node of the transistor switch, the boost signal circuit providing a boost signal responsive to a write enable signal;
- a first delay element;
- a first capacitor in series with the first delay element and having a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element,
- a second delay element;
- and
- a second capacitor in series with the second delay element and having a first end coupled to the bit line voltage node and a second end coupled to second end of the first capacitor through the second delay element.
A device comprising:
- a transistor switch coupled between a bit line voltage node and a ground node;
- a variable delay boost signal circuit coupled to a gate node of the transistor switch, the variable delay boost signal circuit providing a boost signal responsive to a write enable signal, the variable delay boost signal circuit being responsive to a selection signal for selecting one of a plurality of selectable boost signal delays;
- and
- a first capacitor coupled between the gate node of the transistor switch and the bit line voltage node.
A method of sequentially negatively boosting a bit line voltage for writing data to a memory cell, comprising the steps of:
- during a write enable period connecting a bit line voltage node to a ground node through a switch transistor;
- responsive to a boost signal turning the switch transistor off to disconnect the bit line voltage node to the ground node;
- after the switch transistor is turned off, initiating driving the bit line voltage node to a first negative voltage with a capacitor coupled to the bit line voltage node;
- and
- after the write enable period, turning the switch transistor on to reconnect the bit line voltage node to the ground node.
A device comprising:
- a transistor switch coupled between a bit line voltage node and a ground node;
- a boost signal circuit coupled to a gate node of the transistor switch, the boost signal circuit providing a boost signal responsive to a write enable signal;
- a first delay element;
- a first capacitor in series with the first delay element and having a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element;
- a dummy bit line coupled to a dummy write driver, the dummy write driver responsive to a write enable signal to drive the dummy bit line to transition between high and low;
- and
- a detector coupled to the dummy bit line for detecting a transition of the dummy bit line between high and low,
- wherein the boost signal circuit is responsive to an output of the detector for providing the boost signal.
Dependencies are inferred from the claim text.