Memory circuitry with write assist

Memory circuitry comprising:

• a plurality of bit cell means for storing respective data bits;
• write means for writing data bits to target bit cell means of said plurality of bit cell means during a write operation;
• and
• write assist means for lowering a power supply signal supplied to said target bit cell means during said write operation;
• wherein
• said write assist means comprises:
• a plurality of switches connected in series between a first power supply rail having a first power supply signal level and a second power supply rail having a second power supply signal level, said plurality of switches including a header switch having a header gate input and a footer switch having a footer gate input;
• header bias means for generating a header bias signal supplied to said header gate input during said write operation;
• and
• footer bias means for generating a footer bias signal supplied to said footer gate input during said write operation;
• said header bias signal is an analog signal with a signal level intermediate between said first power supply signal level and said second power supply signal level;
• said footer bias signal is an analog signal with a signal level intermediate between said first power supply signal level and said second power supply signal level;
• and
• during said write operation said target bit cell means are supplied with power via a current path through said header switch such that said power supply signal supplied to said target bit cell means during said write operation is controlled by both said header bias signal and said footer bias signal.

A method of operating memory circuitry comprising the steps of:

• storing within a plurality of bit cells respective data bits;
• writing data bits to target bit cells of said plurality of bit cells during a write operation;
• and
• using write assist circuitry to lower a power supply signal supplied to said target bit cells during said write operation;
• wherein
• said write assist circuitry comprises:
• a plurality of switches connected in series between a first power supply rail having a first power supply signal level and a second power supply rail having a second power supply signal level, said plurality of switches including a header switch having a header gate input and a footer switch having a footer gate input;
• header bias circuitry for generating a header bias signal supplied to said header gate input during said write operation;
• and
• footer bias circuitry for generating a footer bias signal supplied to said footer gate input during said write operation;
• said header bias signal is an analog signal with a signal level intermediate between said first power signal level and said second power supply signal level;
• said footer bias signal is an analog signal with a signal level intermediate between said first power supply signal level and said second power supply signal level;
• and
• during said write operation said target bit cells are supplied with power via a current path through said header switch such that said power supply signal supplied to said target bit cells during said write operation is controlled by both said header bias signal and said footer bias signal.