Semiconductor memory device capable of setting an internal state of a NAND flash memory in response to a set feature command
AssigneeKabushiki Kaisha Toshiba
InventorNaoaki Kanagawa
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Abstract
A semiconductor memory device according to an embodiment is provided with a plurality of first latch circuits that latch setting-data at different timings, a plurality of hold circuits provided corresponding to the respective plurality of first latch circuits, each holding data latched by the corresponding first latch circuit, and an address decoder that decodes an address that specifies a destination to hold data. Each of the plurality of hold circuits has one or more holding parts that hold data latched by the corresponding first latch circuit based on a decode signal decoded by the address decoder.
Claims7
A semiconductor memory device comprising:
- a plurality of first latch circuits latching setting-data at different timings;
- a plurality of hold circuits, provided corresponding to the respective plurality of first latch circuits, each holding data latched by the corresponding first latch circuit;
- and
- an address decoder decoding an address that specifies a destination to hold the data,
- wherein each of the plurality of hold circuits has one or more holding parts that hold data latched by the corresponding first latch circuit based on a decode signal decoded by the address decoder.
Dependencies are inferred from the claim text.