Sense amplifier circuitry for resistive type memory

A resistive type memory sense amplifier circuit, comprising:

• a first differential output terminal configured to output a first output signal;
• a second differential output terminal configured to output a second output signal opposite the first output signal;
• a first input terminal coupled to a bit line associated with a resistive type memory cell;
• a second input terminal coupled to a reference line associated with a reference memory cell;
• a first transistor coupled to the second input terminal and to the first differential output terminal, the first transistor being configured to conduct a reference line current;
• a second transistor coupled to the first differential output terminal and arranged in series with the first transistor, the second transistor being configured to conduct a bit line current;
• and
• wherein a voltage level of the first differential output terminal is configured to swing responsive to a delta average current between the reference line current and the bit line current,
• wherein:
• the first transistor is a PMOS type transistor;
• and
• the second transistor is an NMOS type transistor.

A method for sensing bit information stored in a resistive type memory, the method comprising:

• in a pre-charge stage of a sense amplifier circuit, pre-charging, by a pre-charge section, at least a bit line and a reference line;
• in an amplification stage of the sense amplifier circuit, causing a reference line current to flow through the reference line and a bit line current to flow through the bit line;
• in the amplification stage of the sense amplifier circuit, causing a voltage swing at a first differential output terminal responsive to a delta average current between the reference line current and the bit line current;
• and
• in a latch stage of the sense amplifier circuit, latching, by a latch circuit, a logical value “0” or logical value “1” at the first differential output terminal or a second differential output terminal, respectively, using positive feedback of the latch circuit.

A resistive type memory sense amplifier circuit, comprising:

• a first input/output terminal configured to output a first output signal, the first input/output terminal being coupled to a reference line associated with a reference memory cell and to a bit line associated with a resistive type memory cell, the reference line and the bit line being configured to conduct a reference line current;
• a second input/output terminal configured to output a second output signal opposite the first output signal;
• a transistor coupled to the first input/output terminal and to the reference line, the transistor being configured to conduct the reference line current;
• and
• a cross-coupled latch circuit coupled to the first and second input/output terminals, to a positive power supply voltage node, and to a negative power supply voltage node, wherein:
• the latch circuit is configured to latch, based on positive feedback, a logical value “0” or logical value “1” at the first or second input/output terminals, respectively, depending on a bit value stored in the resistive type memory cell;
• the logical value “1” corresponds to one of a positive voltage level of the positive power supply voltage node or a negative voltage level of the negative power supply voltage node;
• the logical value “0” corresponds to the other of the positive voltage level of the positive power supply voltage node or the negative voltage level of the negative power supply voltage node;
• and
• the resistive type memory cell is configured to be re-written by the latched positive voltage level or the latched negative voltage level, and
• wherein a voltage level of the first input/output terminal is configured to swing responsive to the reference line current multiplied by a resistance associated with the resistive type memory cell.