Single package dual channel memory with co-support

A microelectronic package, comprising:

• a support element having first and second oppositely-facing surfaces and a plurality of substrate contacts at the first surface or the second surface, the support element having oppositely-facing north and south edges adjacent to oppositely-facing east and west edges each extending between the north and south edges, the second surface having a southwest region encompassing entire lengths of the south and west edges and extending in orthogonal directions from each of the south and west edges one-third of each distance toward the north edge and toward the east edge, respectively;
• zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, each microelectronic element having a memory storage array and first and second columns of element contacts extending along a front face thereof adjacent and parallel to first and second opposite edges of the front face, respectively, the first and second edges of the zeroth microelectronic element adjacent the south and north edges, respectively, and the first and second edges of the first microelectronic element adjacent the west and east edges, respectively;
• and
• terminals at the second surface electrically coupled with the microelectronic elements via the substrate contacts, the terminals including first terminals at the southwest region, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.