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US 9,070,421 B2Granted
Page buffer circuit and nonvolatile memory device having the same
AssigneeHynix Semiconductor Inc.
InventorSeiichi Aritome
Life of this patent
Estimating the term…
Abstract
A page buffer circuit includes first and second bit lines coupled to a first sensing circuit and with a first space therebetween, and third and fourth bit lines coupled to a second sensing circuit and with the first space therebetween. The second bit line and the third bit line are adjacent to each other with a second space therebetween, and the second space is smaller than the first space.
Claims17
A page buffer circuit comprising:
- a pair of first and second bit lines coupled to a first sensing circuit and with a first space therebetween;
- and
- a pair of third and fourth bit lines coupled to a second sensing circuit and with the first space therebetween,
- wherein the second bit line and the third bit line are adjacent to each other with a second space therebetween, and the second space is smaller than the first space.
1 more element
A nonvolatile memory device comprising:
- a plurality of strings each having a plurality of memory cells coupled in series;
- and
- a plurality of page buffer circuits configured to read data stored in the memory cells,
- wherein each of the page buffer circuits comprises:
- a pair of first and second bit lines coupled to a first sensing circuit and with a first space therebetween;
- and
- a pair of third and fourth bit lines coupled to a second sensing circuit and with the first space therebetween, and
- the second bit line and the third bit line are adjacent to each other with a second space therebetween, and the second space is smaller than the first space.
5 more elements
A page buffer circuit comprising:
- a plurality of bit line pairs each including first and second bit lines adjacent to each other with a first space therebetween;
- a plurality of sensing circuits configured to sense voltage levels of the respective bit line pairs;
- and
- a selection circuit configured to couple the bit line pairs to the sensing circuits in response to first and second control signals,
- wherein adjacent bit lines belonging to different bit line pairs of the bit lines pairs have a second space smaller than the first space therebetween.
2 more elements
A nonvolatile memory device having a page buffer circuit, comprising:
- a plurality of bit line pairs each including first and second bit lines adjacent to each other with a first space therebetween;
- a plurality of sensing circuits configured to sense voltage levels of the respective bit line pairs;
- and
- a selection circuit configured to couple the bit line pairs to the sensing circuits in response to first and second control signals,
- wherein adjacent bit lines belonging to different bit line pairs of the bit lines pairs have a second space smaller than the first space therebetween.
2 more elements
Dependencies are inferred from the claim text.