Memory sharing system and memory sharing method
AssigneeMStar Semiconductors, Inc.
InventorsChunkai Derrick Wei, Po-Sung Huang, Yi Ling Chen, Ming-Chieh Yeh, Chih-Chieh Lee
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Abstract
A memory sharing system includes a master control device, a slave control device and a memory device. The master control device selectively generates a clock signal to the memory device. The slave control device receives and tracks the clock signal via a delay phase locked loop (DLL) to generate and align an output signal with the clock signal. The master control device arbitrates an access right.
Claims16
A memory sharing system, comprising:
- a memory device;
- a master control device, coupled to the memory device via a data bus, for transmitting a clock signal to the memory device;
- and
- a slave control device, coupled to the memory device via the data bus and coupled to the master control device, comprising a delay phase locked loop (DLL), the slave control device receiving the clock signal, with the DLL tracking a phase of the clock signal, wherein the DLL receives the clock signal, and tracks a phase of the clock signal to generate an output signal that is provided to the slave control device accessing the memory device via the data bus;
- wherein the master control device and the slave control device access the memory device via the data bus,
- wherein the memory device is a double data rate dynamic random access memory (DDR-DRAM),
- wherein the slave control device transmits a request signal to the master control device to request an access right of the memory device, and the master control device transmits a grant signal in response to the request signal to grant the access right of the memory device to the slave control device, and
- wherein the access right of the memory device is returned after the slave control device transmits an all-page-close command to the memory device.
A memory sharing method, applicable to a memory sharing system comprising a master control device, a slave control device, a data bus and a memory device, the method comprising:
- the master control device selectively generating a clock signal to the memory device;
- the slave control device receiving the clock signal, and tracking the clock signal utilizing a delay phase locked loop (DLL) to generate an output signal aligned with the clock signal;
- and
- the master control device arbitrating an access right of the memory device,
- wherein the DLL receives the clock signal, and tracks a phase of the clock signal to generate an output signal that is provided to the slave control device accessing the memory device via the data bus,
- wherein the step of the master control device arbitrating an access right of the memory device comprises:
- the slave control device transmitting a request signal to the master control device to request the access right of the memory device;
- the master control device transmitting a grant signal to the slave control device in response to the request signal, and
- the slave control device transmitting an all-page-close command to the memory device before the access right is returned to the master control device.
Dependencies are inferred from the claim text.