Liquid crystal display comprising pixel with charge sharing unit and display driving method thereof

A liquid crystal display (LCD) device comprising:

• a data line for transmitting a data signal;
• a first gate line for transmitting a first gate signal;
• a second gate line for transmitting a second gate signal;
• a first sub-pixel unit electrically connected to the data line and the first gate line, wherein the first sub-pixel unit is used for being written to by a first sub-pixel voltage according to the data signal and the first gate signal;
• a second sub-pixel unit electrically connected to the data line and the first gate line, wherein the second sub-pixel unit is used for being written to by a second sub-pixel voltage according to the data signal and the first gate signal;
• a third sub-pixel unit electrically connected to the data line and the first gate line, wherein the third sub-pixel unit is used for being written to by a third sub-pixel voltage according to the data signal and the first gate signal;
• and
• a reset unit electrically connected to the second gate line, the reset unit being for performing a reset operation on the first sub-pixel voltage of the first sub-pixel unit or the third sub-pixel voltage of the third sub-pixel unit according to the second gate signal.

A method of driving a display for use in driving an LCD device having a 2D/3D switching mechanism and a Multi-domain Vertical Alignment (MVA) mechanism, the LCD device comprising a data line for transmitting a data signal, a first gate line for transmitting a first gate signal, a second gate line for transmitting a second gate signal, a third gate line for transmitting a third gate signal, a first sub-pixel unit electrically connected to the data line and the first gate line, a second sub-pixel unit electrically connected to the data line and the first gate line, a third sub-pixel unit electrically connected to the data line and the first gate line, a charge sharing control unit for controlling charge sharing between the first sub-pixel unit and the third sub-pixel unit according to the second gate signal, and a reset unit for performing a reset operation according to the third gate signal to reset the first sub-pixel voltage or the third sub-pixel voltage, the method comprising:

• in a first period, providing a first gate pulse of the first gate signal to the first gate line for writing the data signal to the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit;
• in a second period following the first period, providing a second gate pulse of the second gate signal to the second gate line for enabling the charge sharing control unit;
• and
• in a third period following the second period, providing a third gate pulse of the third gate signal to the third gate line for enabling the reset unit.

A method of driving a display for use in driving an LCD device having a 2D/3D switching mechanism and a Multi-domain Vertical Alignment (MVA) mechanism, the LCD device comprising a data line for transmitting a data signal, a first gate line for transmitting a first gate signal, a second gate line for transmitting a second gate signal, a third gate line for transmitting a third gate signal, a first sub-pixel unit electrically connected to the data line and the first gate line, a second sub-pixel unit electrically connected to the data line and the first gate line, a third sub-pixel unit electrically connected to the data line and the first gate line, a charge sharing control unit for controlling charge sharing between the first sub-pixel unit and the third sub-pixel unit according to the second gate signal, and a reset unit for performing a reset operation according to the third gate signal to reset the first sub-pixel voltage or the third sub-pixel voltage, the method comprising:

• in a first period, providing a third gate pulse of the third gate signal to the third gate line for enabling the reset unit;
• in a second period following the first period, providing a first gate pulse of the first gate signal to the first gate line for writing the data signal to the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit;
• and
• in a third period following the second period, providing a second gate pulse of the second gate signal to the second gate line for enabling the charge sharing control unit.