Address-selectable charging of capacitive devices

A drive circuit for a capacitive device that comprises a first operational state and a second operational state, said drive circuit comprising:

• a first transistor having a gate, a drain, and a source, wherein said gate is coupled to a row line, and one of said source and drain is coupled to a column line;
• a capacitor having a first terminal and a second terminal, wherein said first conductive terminal is coupled to the row line and the second conductive terminal couples to the other of the first transistor's source and drain and also is coupled to the capacitive device;
• and
• a transistor circuit coupled to said column line, said transistor circuit comprising a second transistor and a third transistor, each of the second and third transistors having a gate, a drain, and a source;
• wherein one of the drain and source of the second transistor is tied to a first voltage and one of the drain and source of the third transistor is tied to a second voltage that is different than the first voltage, and the second transistor's gate is configured to receive a first column enable signal and said third transistor's gate is configured to receive a second column enable signal;
• wherein a variable voltage between said first and second voltage is caused to be applied to one terminal of said capacitive device, said variable voltage is a function of at least the relative timing of falling edges of said first and second column enable signals and a falling edge of a row pulse on said row line.

A drive circuit for a capacitive device that comprises a first operational state and a second operational state, said drive circuit comprising:

• a first transistor having a gate, a drain, and a source, wherein said gate is coupled to a row line;
• a second transistor having a gate, a drain and a source, wherein one of said second transistor's drain and source is coupled to one of the source and drain of the first transistor thereby coupling the first and second transistors in series, and wherein the gate of the second transistor is coupled to said column line;
• a capacitor having a first terminal and a second terminal, wherein said first conductive terminal is coupled to the row line and the second conductive terminal couples to the other of the second transistor's source and drain and also is coupled to the capacitive device;
• and
• wherein the capacitive device is caused to transition from the first operational state to the second operational state by a row pulse being asserted on the row line and a column pulse asserted on the column enable signal commensurate with the assertion of the row pulse, said column pulse deasserted before the row pulse is deasserted, wherein said capacitive device is caused to transition from the first operational state to the second operational state upon deassertion of the row pulse.