Methods and systems to reduce display artifacts when changing display clock rate
AssigneeATI Technologies ULC
InventorsCollis Quinn Carter, Natan Shtutman, Jonathan Wang, Stephen Ho, Nicholas James Chorney
Life of this patent
Estimating the term…
Abstract
Methods, systems, and computer readable media embodiments for reducing or eliminating display artifacts caused by on-the-fly changing of the display clock are disclosed. According to an embodiment of the present invention, a method includes, changing a rate of a display clock, and adapting a display data processing pipeline clocked by the display clock to prevent a substantial change in a pixel output rate from the display data processing pipeline based upon the changing.
Claims21
A method, comprising:
- changing a rate of a display clock;
- adapting a display data processing pipeline clocked by the display clock to prevent a substantial change in a pixel output rate from the display data processing pipeline based upon the changing, wherein a delay in the display data processing pipeline remains constant by adjusting a number of compensation pipeline stages;
- and,
- writing an output data from the display data processing pipeline into a buffer at the pixel output rate.
A system comprising:
- a host processor;
- a clock source configured to change a rate of a display clock;
- a rate generating module configured to embed a signal corresponding to a pixel clock in a display data processing pipeline clocked by the display clock;
- and
- a display pipeline adjuster configured to adapt the display data processing pipeline to prevent a substantial change in a pixel output rate from the display data processing pipeline based upon said change of the rate of the display clock, wherein the embedded signal changes a number of compensation pipeline stages in the display data processing pipeline to maintain a constant delay in the display data processing pipeline.
A non-transitory computer readable medium storing instructions, wherein the instructions when executed are adapted to perform a method comprising:
- changing a rate of a display clock;
- adapting a display data processing pipeline clocked by the display clock to prevent a substantial change in a pixel output rate from the display data processing pipeline based upon the changing, wherein a delay in the display data processing pipeline remains constant by adjusting a number of compensation pipeline stages;
- and,
- writing an output data from the display data processing pipeline into a buffer at the pixel output rate.
Dependencies are inferred from the claim text.