Code updates in processing systems

A system comprising:

• a switching device;
• a main processor;
• a first memory device communicatively connected to the main processor;
• a second memory device communicatively connected to the first memory device, wherein a second location of the second memory device is communicatively connected with a first location of the first memory device through the switching device;
• and
• a sub-system processor communicatively connected to the main processor and the second memory device wherein the sub-system processor is operative to
• boot a first image of a code, receive a second image of the code, perform a security and reliability check of the second image of the code;
• determine whether the security and reliability check of the second image of the code is successful;
• and
• responsive to determining that the security and reliability check of the second image of the code is successful,
• store the second image of the code in the first location of the first memory device,
• designate the second image of the code as an active image by changing a state of a switching device from a first state to a second state, the switching device corresponding to the first location of the first memory device and to the second location of the second memory device, and
• send the second image of the code to the second location of the second memory device.