Securing microprocessors against information leakage and physical tampering
AssigneeBlueRISC, Inc.
InventorsCsaba Andras Moritz, Saurabh Chheda, Kristopher Carver
Life of this patent
Estimating the term…
Loading patent…
AssigneeBlueRISC, Inc.
InventorsCsaba Andras Moritz, Saurabh Chheda, Kristopher Carver
Estimating the term…
A processor system comprising: performing a compilation process on a computer program; encoding an instruction with a selected encoding; encoding the security mutation information in an instruction set architecture of a processor; and executing a compiled computer program in the processor using an added mutation instruction, wherein executing comprises executing a mutation instruction to enable decoding another instruction. A processor system with a random instruction encoding and randomized execution, providing effective defense against offline and runtime security attacks including software and hardware reverse engineering, invasive microprobing, fault injection, and high-order differential and electromagnetic power analysis.
A method comprising:
A system comprising:
A method comprising:
A system comprising:
A method comprising:
A system comprising:
Dependencies are inferred from the claim text.