US 9,069,926 B2 · Standard cells having transistors annotated for gate-length biasing

Abstract

Methods, layouts and chip design layouts that use annotations for communicating gate-length biasing amounts to post-layout tools are disclosed. One method includes receiving a chip design layout designed to includes select ones of a plurality of nominal cell layouts and an annotated cell layout. The chip design layout is defined by a plurality of layers and the plurality of nominal cell layouts define transistors, wherein each of the plurality of nominal cell layouts define nominal length transistors, and the annotated cell layout also defines transistors. The annotated cell layout is associated with an annotation layer that identifies a gate-length biasing to be applied to at least one transistor of the annotated cell layout. The gate-length biasing identifies an amount of change for a gate length and not width-sizing of a gate width of the at least one transistor of the annotated cell layout. The annotation layer is used to communicate design-specific directives that require implementation. The method uses a processor to process the chip design layout, with reference to the annotation layer, to apply the gate-length biasing to the annotated cell of the chip design layout.

Claims30

Dependent claims

A standard cell library used to design a layout, wherein a processor is used to produce a biased layout from the layout for fabricating a semiconductor device on a wafer, the layout stored on a non-transitory computer readable storage, comprising:

the layout includes cell layouts from the standard cell library, the cell layouts include a plurality of layers, wherein at least one transistor in at least one cell layout is identified by an annotation layer, and the annotation layer itself identifies gate-length biasing to be applied to the at least one transistor of the at least one cell layout when the processor produces the biased layout, using the annotation layer, after the layout has been designed, wherein the gate-length biasing defines an amount of change to a gate length that is not width-sizing of a gate width of the at least one transistor;
wherein the amount of change is a positive or a negative amount of change for the gate length, and the amount of change is represented as nanometer values from about 1 nanometer to about 10 nanometers, the gate-length biasing identified by the annotation layer represents design-specific directives that require implementation, and
wherein fabricating the semiconductor device includes making one or more masks from the biased layout, the fabricating resulting in at least one fabricated feature on the wafer.

A chip design layout to be gate-length biased, stored on a non-transitory computer readable storage, comprising

the chip design layout designed to include at least one cell layout that contains at least one transistor, the chip design layout includes a plurality of layers,
an annotation layer being one of the plurality of layers, the annotation layer identifying the at least one cell layout of the chip design layout, the annotation layer itself identifies gate-length biasing for the at least one transistor, the gate-length biasing provides for an amount of change to a gate length that is not width-sizing of a gate width of the at least one transistor, wherein gate-length biasing of the chip design layout is performed after the chip design layout has been designed and a result of the gate-length biasing is a biased chip design layout;
wherein the gate-length biasing identified by the annotation layer represents design-specific directives that require implementation, the biased chip design layout being used to make one or more masks implemented to fabricate at least one feature on a wafer to define an integrated circuit chip.

A method, comprising:

receiving a chip design layout designed to includes select ones of a plurality of nominal cell layouts and an annotated cell layout, the chip design layout defined by a plurality of layers, wherein the plurality of nominal cell layouts define transistors, each of the plurality of nominal cell layouts defining nominal length transistors, and the annotated cell layout also defines transistors, the annotated cell layout being associated with an annotation layer that identifies a gate-length biasing to be applied to at least one transistor of the annotated cell layout, the gate-length biasing identifies an amount of change for a gate length and not width-sizing of a gate width of the at least one transistor of the annotated cell layout, the annotation layer being used to communicate design-specific directives that require implementation;
using a processor to process the chip design layout, with reference to the annotation layer, to apply the gate-length biasing to the annotated cell of the chip design layout, the processing produces a biased chip design layout, wherein the gate-length biasing is applied post-layout of the received chip design layout;
and
using the biased chip design layout to produce one or more masks to manufacture an integrated circuit from a semiconductor wafer.

1 more element

Dependencies are inferred from the claim text.

Standard cells having transistors annotated for gate-length biasing

Life of this patent

Standard cells having transistors annotated for gate-length biasing

Life of this patent

Abstract

Claims30