ESD protection circuit cell
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorBo-Ting Chen
Life of this patent
Estimating the term…
Abstract
A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2. The protection circuit includes a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus connected to Vdd2 and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provided, from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus.
Claims20
In an integrated circuit (IC) having a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2, a protection circuit comprising:
- a first power bus connected to Vdd2;
- a first ground bus connected to a ground supply voltage, arranged so that a distance between the first power bus and the first ground bus matches a distance between a power bus of the driven device and a ground bus of the driven device;
- a first device from the group consisting of a P-diode and a gate-Vdd PMOS, the first device coupled between the first power bus and the input of the driven device, the input of the driven device coupled by way of a resistor to the output of the driving device, the first device having first and second N+ regions connected by a third N+ region to form a U-shape with the third N+ region adjacent to an edge of the protection circuit having the first power bus;
- and
- a second device corresponding to the first device, from the group consisting of an N-diode and a grounded gate NMOS, the first and second devices arranged symmetrically about horizontal and vertical centerlines of the protection circuit, the second device coupled between the input of the driven device and the ground bus.
An integrated circuit (IC) comprising:
- a driving device with a first supply voltage Vdd1 and an output,
- a driven device having an input and a second supply voltage Vdd2,
- a protection circuit for the IC, the protection circuit including:
- a P-diode coupled between a first power bus coupled to Vdd2 and the input of the driven device, the P diode having first and second N+ regions connected by a third N+ region to form a U-shape with the third N+ region adjacent to an edge of the protection circuit having the first power bus, and a P+ region between the first and second N+ regions, the N+ regions connected to Vdd2, the P+ region connected to the input of the driven device, the input of the driven device coupled by way of a resistor to the output of the driving device;
- and
- an N-diode, the P diode and N diode arranged symmetrically about horizontal and vertical centerlines of the protection circuit, the N-diode coupled between the input of the driven device and a ground bus,
- wherein a distance between the first power bus and the first ground bus matches a distance between a power bus of the driven device and a ground bus of the driven device.
An integrated circuit (IC), comprising:
- a driving device with a first supply voltage Vdd1 and an output;
- a driven device having an input and a second supply voltage Vdd2;
- a protection circuit including:
- a gate-Vdd PMOS coupled between a first power bus connected to Vdd2 and the input of the driven device, the gate-Vdd PMOS having first and second N+ regions connected by a third N+ region to form a U-shape with the third N+ region adjacent to an edge of the protection circuit having the first power bus, and a pluralitv of P+ regions between the first and second N+ regions, the input of the driven device coupled by way of a resistor to the output of the driving device;
- and
- a grounded gate NMOS (GGNMOS) coupled between the input of the driven device and a ground bus, the GGNMOS and gate-Vdd PMOS arranged symmetrically about horizontal and vertical centerlines of the protection circuit;
- and
- wherein the protection circuit occupies a first region having a cell height that is the same as a cell height of a second region having the input of the driven device.
Dependencies are inferred from the claim text.