Modeling memory cell skew sensitivity

A method comprising:

• designating a cell mismatch parameter for a memory cell including a plurality of transistors and an initial value of a transistor mismatch parameter for each of the plurality of transistors;
• determining a critical current sensitivity parameter for each of the plurality of transistors based on the transistor mismatch parameters in a computing apparatus;
• distributing the cell mismatch parameter across the plurality of transistors in the computing apparatus to update the individual transistor mismatch parameters for each of the plurality of transistors based on the critical current sensitivity parameters and the cell mismatch parameter;
• iterating the determining and the distributing until a change in the individual transistor mismatch parameters for a given iteration is less than a predetermined threshold;
• simulating the memory cell based on the individual transistor mismatch parameters to generate a simulation result;
• determining a boundary cell mismatch parameter by determining simulation results for a plurality of cell mismatch parameters;
• and
• determining a cell disturb margin of the memory cell based on the boundary cell mismatch parameter.

A computing apparatus, comprising a processor programmed with instructions for performing a method for simulating a memory cell having a plurality of transistors, the method comprising:

• designating a cell mismatch parameter of the memory cell and an initial value of a transistor mismatch parameter for each of the plurality of transistors;
• determining a critical current sensitivity parameter for each of the plurality of transistors based on the transistor mismatch parameters in a computing apparatus;
• distributing the cell mismatch parameter across the plurality of transistors in the computing apparatus to update the individual transistor mismatch parameters for each of the plurality of transistors based on the critical current sensitivity parameters and the cell mismatch parameter;
• and
• simulating the memory cell based on the individual transistor mismatch parameters to generate a simulation result.