Verification apparatus for semiconductor integrated circuit, verification method for semiconductor integrated circuit, and program therefor
AssigneeKabushiki Kaisha Toshiba
InventorsNaoyuki Kawabe, Tetsuaki Utsumi
Life of this patent
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Abstract
The verification apparatus for a semiconductor integrated circuit verifies a logic equivalence before and after modification to the circuit by replacing a memory with a divisional memory model that agrees with the memory in number of input and output pins and verifying logics at an input and an output thereof.
Claims12
A verification apparatus for a semiconductor integrated circuit, comprising:
- a processor that verifies a logic equivalence before and after modification to the circuit by:
- replacing a memory with a divisional memory model that agrees with the memory in number of input and output pins, wherein the divisional memory model comprises a plurality of divisional memories that have a smaller capacity than the memory and are addressed by a part of an address signal that designates an address of the memory;
- and
- verifying logics at an input and an output of the circuit.
A verification method for a semiconductor integrated circuit, the method comprising:
- verifying, by a verification apparatus comprising computer hardware, a logic equivalence before and after modification to the circuit by:
- replacing a memory with a divisional memory model that agrees with the memory in number of input and output pins, wherein the divisional memory model comprises a plurality of divisional memories that have a smaller capacity than the memory and are addressed by a part of an address signal that designates an address of the memory;
- and
- verifying logics at an input and an output of the circuit.
A program comprising instructions stored on a non-transitory physical computer storage, the instructions configured to implement a method of performing verification of a semiconductor integrated circuit by a computer, the program comprising:
- performing, by using a verification apparatus, a verification of a logic equivalence before and after modification to the circuit is verified by:
- replacing a memory with a divisional memory model that agrees with the memory in number of input and output pins, wherein the divisional memory model comprises a plurality of divisional memories that have a smaller capacity than the memory and are addressed by a part of an address signal that designates an address of the memory;
- and
- verifying logics at an input and an output of the circuit.
Dependencies are inferred from the claim text.