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US 9,069,896 B2Granted
Data processor device for handling a watchpoint and method thereof
AssigneeFreescale Semiconductor, Inc.
InventorsJeffrey W. Scott, William C. Moyer
Life of this patent
Estimating the term…
Abstract
During a debug mode of operation of a data processor, it is determined at the data processor that a watchpoint event has occurred, and in response, an operating condition of a trace FIFO that stores trace information not yet communicated to a debugger is changed. For example, the occurrence of a FIFO flush watchpoint results in trace information being flushed from the trace FIFO before the trace information has been communicated to a trace analyzer.
Claims20
A method comprising:
- enabling a trace mode of operation of an integrated circuit;
- storing first trace information at a memory of the integrated circuit in response to the trace mode of operation being enabled;
- and
- flushing the first trace information from the memory to prevent the first trace information from being provided for trace analysis, in response to detecting an occurrence of a watchpoint of a first type during the trace mode of operation, wherein flushing the memory does not change the trace mode of operation, and detecting the occurrence of the watchpoint occurs after storing of the first trace information.
1 more element
A device comprising:
- an integrated circuit comprising a trace module, the trace module comprising an output, the trace module to provide trace information of a data processor at the output for trace analysis;
- a watchpoint module comprising an output, the watchpoint module to provide a flush indicator at the output in response to detecting an occurrence of a watchpoint event;
- and
- a memory module coupled to the output of the trace module and to the output of the watchpoint module, the memory module to flush buffered trace information stored at the memory module so that it is not provided for trace analysis in response to the flush indicator.
1 more element
A method comprising:
- enabling a trace mode of operation of an integrated circuit by enabling operation of a debug module of the integrated circuit;
- storing, by the debug module, trace information at a memory of the integrated circuit in response to the trace mode of operation being enabled, wherein trace information stored at the memory is available for access in response to an access request received at control circuitry of the debug module;
- providing a first portion of the trace information to an interconnect external the debug module in response to receiving, at the control circuitry, an access request;
- removing the first portion of the trace information from the trace information in response to providing the first portion, wherein portions of the trace information removed from the trace information are no longer part of the trace information;
- and
- subsequent to removing the first portion, flushing, by the debug module, the trace information in response to the debug module detecting an occurrence of a watchpoint of a first type during the trace mode of operation, wherein flushing the trace information from the memory does not change the trace mode of operation, and flushing the trace information from the memory results in removal of all trace information from the memory without the trace information being provided to the interconnect.
3 more elements
Dependencies are inferred from the claim text.