NUMA-aware scaling for network devices
AssigneeIntel Corporation
InventorYadong Li
Life of this patent
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Abstract
The present disclosure describes a method and apparatus for network traffic processing in a non-uniform memory access architecture system. The method includes allocating a Tx/Rx Queue pair for a node, the Tx/Rx Queue pair allocated in a local memory of the node. The method further includes routing network traffic to the allocated Tx/Rx Queue pair. The method may include designating a core in the node for network traffic processing. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
Claims17
A system comprising one or more storage mediums having stored thereon, individually or in combination, instructions that when executed by one or more processors cause the one or processors to:
- automatically allocate a single respective receive queue per respective set of multiple sets of multiple processor cores, each single respective receive queue to enqueue respective entries for respective received network packets based on a hash of multiple header fields of the respective received network packets;
- and
- for each respective set of the sets of multiple processor cores, cause designation of a single respective core of the multiple processor cores to receive interrupts and cause an interrupt vector to be set with affinity to the single respective core.
A system, comprising:
- multiple sets of multiple processor cores;
- and
- a network adapter;
- and
- a network adapter device driver comprising one or more storage mediums having stored thereon, individually or in combination, instructions that when executed by one or more processors cause the one or more processors to:
- automatically allocate a single respective receive queue per respective set of multiple sets of multiple processor cores, each single respective receive queue to enqueue respective entries for respective received network packets based on a hash of multiple header fields of the respective received network packets;
- and
- for each respective set of the sets of multiple processor cores, cause designation of a single respective core of the multiple processor cores to receive interrupts and cause an interrupt vector to be set with affinity to the single respective core.
A system comprising one or more storage mediums having stored thereon, individually or in combination, instructions that when executed by one or more processors cause the one or more processors to:
- determine a same number of receive queues per respective set of multiple sets of multiple processor cores, each respective receive queue to enqueue respective entries for respective received network packets based on a hash of multiple network packet header fields of the respective received network packets;
- and
- allocate the determined same number of receive queues per respective set of multiple processor cores.
A system, comprising:
- multiple sets of multiple processor cores;
- and
- a network adapter;
- and
- a network adapter device driver comprising one or more storage mediums having stored thereon, individually or in combination, instructions that when executed by one or more processor cause the one or more processors to:
- determine a same number of receive queues per respective set of multiple sets of multiple processor cores, each respective receive queue to enqueue respective entries for respective received network packets based on a hash of multiple network packet header fields of the respective received network packets;
- and
- allocate the determined same number of receive queues per respective set of multiple processor cores.
Dependencies are inferred from the claim text.