Memory parametric improvements
AssigneeInphi Corporation
InventorsDavid T. Wang, Andrew Burstein
Life of this patent
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Abstract
An integrated circuit memory interface device coupled to a dynamic random access memory device is provided. The device includes an address match table. The address match table includes a plurality of first addresses. Each of the first addresses is associated with a memory cell having a refresh characteristic outside of a specification for a DRAM device. The device has a plurality of second addresses. Each of the second addresses is associated with a refresh characteristic within a specification of the DRAM device and outside of a predetermined refresh characteristic range characterized to eliminate accesses to memory cells not meeting the predetermined refresh characteristic range.
Claims18
A system comprising:
- a dynamic random access memory device;
- a memory interface device coupled to the dynamic random access memory device, the memory interface device comprising:
- an address match table comprising:
- a plurality of first addresses, each of the first addresses associated with a memory cell having a refresh characteristic outside of a specification for a DRAM device;
- a plurality of second addresses, each of the second addresses associated with a refresh characteristic within a specification of the DRAM device and outside of a predetermined refresh characteristic range characterized to eliminate accesses to memory cells not meeting the predetermined refresh characteristic range,
- wherein the predetermined refresh characteristic range is characterized to prioritize accesses to memory cells having improved parametric values.
An integrated circuit memory interface device coupled to a dynamic random access memory device, the memory interface device comprising:
- an address match table comprising:
- a plurality of first addresses, each of the first addresses associated with a memory cell having a refresh characteristic outside of a specification for a DRAM device;
- and
- a plurality of second addresses, each of the second addresses associated with a refresh characteristic within a specification of a DRAM device and outside of a predetermined refresh characteristic range characterized to eliminate accesses to memory cells not meeting the predetermined refresh characteristic range,
- wherein the predetermined refresh characteristic range is characterized to prioritize accesses to memory cells having improved parametric values.
Dependencies are inferred from the claim text.