Reducing microprocessor performance loss due to translation table coherency in a multi-processor system

A method comprising:

• fetching first instructions for execution in a multi-processor system;
• associating a first instruction timestamp with each of the first instructions, wherein the first instruction timestamp is derived from a first timestamp in a master-tag register;
• receiving a multi-processor coherency operation in a first microprocessor of the multi-processor system, wherein the multi-processor coherency operation indicates a purge operation for translation lookaside buffers in the multi-processor system;
• incrementing the first timestamp value in a master-tag register to form a second timestamp value after receiving the multi-processor coherency operation;
• copying the second timestamp value to a source-tag register;
• fetching, by an instruction fetch unit in the first microprocessor, second instructions for execution in the multiprocessor system;
• associating a second instruction timestamp with each of the second instructions, wherein the second instruction timestamp is derived from the second timestamp value in the source-tag register;
• enabling an emulated purge mechanism, wherein the emulated purge mechanism performs operations including,
• determining that the second instruction timestamp values associated with the second instructions are equal to the second timestamp value in the master-tag register;
• and
• suppressing, by the emulated purge mechanism, hits in the translation lookaside buffers for the second instructions;
• determining that the first instructions are complete;
• after determining the first instructions are complete, purging entries in the translation lookaside buffers;
• and
• disabling the emulated purge mechanism.