Fully parallel encoding method and fully parallel decoding method of memory system

A method of a fully parallel decoding of a memory system, the memory system comprising a memory cell, a reading circuit, an encoder and a fully parallel decoder, the method comprising the steps of:

• (a) reading data from the memory cell via the reading circuit;
• (b) deriving a plurality of syndromes from a parity check matrix and the data, wherein a factorized matrix used by the encoder is a sub-matrix of the parity check matrix, the parity check matrix corresponding to a hardware circuit of a syndrome calculator of the fully parallel decoder, the factorized matrix corresponding to a portion of the hardware circuit, wherein the data is encoded by the encoder using the portion of the hardware circuit;
• (c) deriving an error locator polynomial from the syndromes;
• (d) substituting a plurality of primitive elements to the error locator polynomial for obtaining a plurality of roots of the error locator polynomial;
• and
• (e) finding an error location from the roots of the error locator polynomial.

A memory system, comprising:

• an encoder for utilizing an encoding matrix to encode an input data for generating a codeword;
• a memory cell for storing from the codeword;
• a write circuit electrically connected to the encoder for transmitting the codeword to the memory cell;
• a read circuit for reading the data from the memory cell;
• and
• a decoder for utilizing a parity check matrix to decode a data read from the memory cell;
• wherein the encoding matrix is the multiplication of a plurality of factorized matrices, and one of the plurality of factorized matrices is a sub-matrix of the parity check matrix.