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US 9,069,690 B2Granted
Concurrent page table walker control for TLB miss handling
AssigneeIntel Corporation
InventorsGur Hildesheim, Chang Kian Tan, Robert S. Chappell, Rohit Bhatia
Life of this patent
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Abstract
In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.
Claims19
A processor comprising:
- at least one execution unit to execute instructions;
- and
- a page miss handler including a plurality of paging caches and a first walker structure to receive, responsive to a miss in a translation lookaside buffer (TLB) of the processor, at least a portion of a first linear address and to obtain a corresponding portion of a physical address from one or more paging structures stored in a system memory, a second walker structure to operate concurrently with the first walker structure, and a concurrent walker logic to prevent the first walker structure from storing the obtained physical address portion in one of the paging caches responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker structure, wherein the first walker structure is to access a first paging structure using a first segment of the first linear address portion and a value of a control register and to store a first accessed entry from the first paging structure in a first paging cache, based on a state of a first field of a status register associated with the first walker structure and to access a second paging structure using the first accessed entry and a second segment of the first linear address portion and to store a second accessed entry from the second paging structure in a second paging cache, based on a state of a second field of the status register associated with the first walker structure.
A method comprising:
- initializing a first walker of a page miss handler of a processor to perform a page walk to determine a physical address for a linear address;
- and
- setting a first status indicator in a first field of a status register associated with a first paging cache, the status register including a plurality of fields each associated with one of a plurality of walkers of the page miss handler, the first field associated with the first walker to indicate that the first walker is enabled to store a portion of a physical address obtained in an entry of the first paging cache if another walker of the page miss handler is not concurrently performing a page walk for the linear address, and otherwise setting the first status indicator to indicate the first walker is not enabled to store the obtained physical address portion, wherein the first walker is to access a first paging structure using a first portion of the linear address and a value of a control register and to store a first accessed entry from the first paging structure in the first paging cache, based on the status indicator in the first field of the status register associated with the first walker and to access a second paging structure using the first accessed entry and a second portion of the linear address and to store a second accessed entry from the second paging structure in a second paging cache, based on a status indicator in a second field of the status register associated with the first walker.
A system comprising:
- a multicore processor including a plurality of cores each having a memory execution unit including a plurality of walkers to perform page walks to a system memory responsive to misses in a translation lookaside buffer (TLB) of the multicore processor, and a control logic to prevent a first walker from storing a physical address portion obtained from the system memory in a paging cache when the first walker and a second walker perform concurrent page walks for a common linear address segment, wherein the first walker is to access a first paging structure using a first linear address segment and a value of a control register and to store a first accessed entry from the first paging structure in the paging cache, based on a state of a first field of a status register associated with the first walker and to access a second paging structure using the first accessed entry and a second linear address segment and to store a second accessed entry from the second paging structure in a second paging cache, based on a state of a second field of the status register associated with the first walker;
- and
- a dynamic random access memory (DRAM) coupled to the multicore processor, the DRAM comprising the system memory.
Dependencies are inferred from the claim text.