US 9,069,688 B2Granted

Dynamic optimization of back-end memory system interface

AssigneeSanDisk Technologies LLC

InventorsChun Sing Jackson Chung, Steven Shisan Cheng

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Abstract

Techniques are presented for dynamically optimizing the performance of the controller-memory (or “back-end”) interface of a non-volatile memory system. Memory systems are usually designed to have a certain amount of error tolerance for error that can then be corrected by ECC. In may circumstances, such as when a device is new, the ECC capabilities of the system exceed what is needed to correct data storage errors. In these circumstances the memory system internally allots a non-zero portion of this error correction capacity to the back-end interface. This allows for the interface to operate at, for example, higher speed or lower power, even though this will likely lead to transmission path error. The system can also calibrate the back-end interface to determine that amount of error that result from various operating conditions, allowing the operating parameters of the back-end interface to be set according to amount of error that is allotted to the transfer process.

Claims29

Dependent claims

A method of operating a non-volatile memory system, the non-volatile memory system including a controller circuit having a memory interface, a memory circuit having an array of non-volatile memory cells and a controller interface, and a bus structure connected to the memory interface of the controller circuit and to the controller interface of the memory circuit for the transfer of data and commands therebetween, wherein the memory system can tolerate a first, non-zero amount of accumulated data error from when a unit of data is transferred from the controller to be written to the memory array until the unit of data is received at the controller after subsequently being read back from the memory array, the method comprising:

allotting by the controller circuit of a first, non-zero portion of the first amount of accumulated data error to the transfer of data between the controller circuit and the memory circuit via the bus structure, the remainder of the first amount of accumulated data error being allotted to write, storage, and read of data on the memory circuit;
and
setting by the controller circuit of the transfer characteristics between the controller circuit and the memory circuit to operate to allow up to the first portion of the first amount of accumulated data error.

A method of operating a non-volatile memory system having a controller circuit and a memory circuit including an array of non-volatile memory cells, the method comprising:

operating the non-volatile memory system to tolerate a total, non-zero amount of accumulated data error from when a unit of data is transferred from the controller to be written to the memory array until the unit of data is received at the controller after subsequently being read back from the memory array;
performing by the controller circuit of a transmission error calibration by performing, for each of a plurality of values for each of one or more operating parameters for a bus structure connecting the controller with the memory circuit, a process including:
transferring a data set of a known data pattern from the controller through transmission circuitry on the controller to the bus structure;
receiving the data set from the bus structure through receiving circuitry on the memory circuit;
storing the data set as received in buffer memory on the memory circuit;
transferring the data set as stored in buffer memory on the memory circuit, and without being written into the array, through transmission circuitry on the memory circuit to the bus structure;
receiving the data set from the bus structure through receiving circuitry on the controller;
performing a comparison of the data set as received with the known pattern;
and
based on the comparison, determining the amount of error associated with the transmission process for the used one or more operating parameter;
and
subsequently operating the memory system to allow a first, non-zero portion of the total amount of accumulated data error in the transmission of data between the controller circuit and the memory circuit, wherein the controller circuit selects values of the operating parameters according to the transmission error calibration process based on the determined amounts of error associated with the transmission process.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/087,640Filed 15 Apr 2011
Published: US 2012/0266048 A118 Oct 2012
Granted: 30 Jun 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G06F 11/10
Error detection or correction by redundancy in data representation, e.g. by using checking codes: adding special bits or symbols to the coded…
G06F 11/08
Responding to the occurrence of a fault, e.g. fault tolerance: error detection or correction by redundancy in data representation, e.g. by using…
G06F
Computing and data processing