Coherent proxy for attached processor

A data processing system, comprising:

• a primary coherent system including:
• a system fabric;
• a plurality of processing units coupled to the system fabric for communication there between, wherein a processing unit among the plurality of processing units includes:
• at least one processor core;
• a cache coupled to the processor core;
• and
• a coherent attached processor proxy (CAPP), including:
• transport circuitry having a first interface configured to support communication with a system fabric of a primary coherent system a second interface configured to support communication with an attached processor (AP) that is external to the primary coherent system and that is coupled to the CAPP, wherein the AP includes a cache memory that holds copies of memory blocks belonging to a coherent address space of the primary coherent system;
• snooper circuitry that services snooped memory access requests received from the system fabric on behalf of and in stead of the AP;
• and
• master circuitry that manages memory access requests within the primary coherent system on behalf of and in the stead of the AP, wherein the master circuitry, responsive to receiving a memory access request from the AP and an expected coherence state of a target address of the memory access request with respect to the cache memory of the AP, determines a coherence state of the target address with respect to the CAPP and determines whether or not the expected coherence state matches the coherence state determined by the CAPP, and wherein the master circuitry, responsive to determining that the expected coherence state matches the coherence state determined by the CAPP, issues a memory access request corresponding to that received from the AP on the system fabric of the primary coherent system, and responsive to determining that the expected coherence state does not match the coherence state determined by the CAPP, transmits a failure message to the AP without issuing on the system fabric a memory access request corresponding to that received from the AP.

A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a coherent attached processor proxy (CAPP), including:
• transport circuitry having a first interface configured to support communication with a system fabric of a primary coherent system a second interface configured to support communication with an attached processor (AP) that is external to the primary coherent system and that is coupled to the CAPP, wherein the AP includes a cache memory that holds copies of memory blocks belonging to a coherent address space of the primary coherent system;
• snooper circuitry that services snooped memory access requests received from the system fabric on behalf of and in stead of the AP;
• and
• master circuitry that manages memory access requests within the primary coherent system on behalf of and in the stead of the AP, wherein the master circuitry, responsive to receiving a memory access request from the AP and an expected coherence state of a target address of the memory access request with respect to the cache memory of the AP, determines a coherence state of the target address with respect to the CAPP and determines whether or not the expected coherence state matches the coherence state determined by the CAPP, and wherein the master circuitry, responsive to determining that the expected coherence state matches the coherence state determined by the CAPP, issues a memory access request corresponding to that received from the AP on the system fabric of the primary coherent system, and responsive to determining that the expected coherence state does not match the coherence state determined by the CAPP, transmits a failure message to the AP without issuing on the system fabric a memory access request corresponding to that received from the AP.