Unified streaming multiprocessor memory
AssigneeNVIDIA Corporation
InventorWilliam James Dally
Life of this patent
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Abstract
One embodiment of the present invention sets forth a technique for providing a unified memory for access by execution threads in a processing system. Several logically separate memories are combined into a single unified memory that includes a single set of shared memory banks, an allocation of space in each bank across the logical memories, a mapping rule that maps the address space of each logical memory to its partition of the shared physical memory, a circuitry including switches and multiplexers that supports the mapping, and an arbitration scheme that allocates access to the banks.
Claims18
A method for accessing a unified memory, the method comprising:
- arbitrating access requests for the unified memory, wherein the unified memory is configured for aligned access requests and unaligned access requests;
- multiplexing data from different banks of the unified memory to process the aligned access requests;
- and
- switching data from different banks of the unified memory to process the unaligned access requests, wherein different portions of the unified memory are allocated for different logical memories and the different logical memories include constant registers.
A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to access a unified memory, by performing the steps of:
- arbitrating access requests for the unified memory, wherein the unified memory is configured for aligned access requests and unaligned access requests;
- multiplexing data from different banks of the unified memory to process the aligned access requests;
- and
- switching data from different banks of the unified memory to process the unaligned access requests, wherein different portions of the unified memory are allocated for different logical memories and the different logical memories include constant registers.
A system for accessing a unified memory, the system comprising:
- banks of memory configured to store data for the unified memory;
- a multiplex unit configured to direct the data for aligned and unaligned access requests;
- a crossbar interconnect coupled to the multiplex unit and the banks of memory and configured to direct the data for unaligned access requests by switching the data between different banks of the banks of memory;
- a mode selection unit coupled between the multiplex unit and the crossbar interconnect and input ports of multiple execution units;
- and
- a unified memory access control coupled to the at least one memory bank, the multiplex unit, the crossbar interconnect, and the mode selection unit and configured to arbitrate access requests for the unified memory and configure the multiplex unit, the crossbar interconnect, and the mode selection unit for aligned access requests and unaligned access requests.
Dependencies are inferred from the claim text.