Integrated level shifting latch circuit and method of operation of such a latch circuit

A method of operating an integrated level shifting latch circuit configured to receive an input signal in a first voltage domain and generate an output signal in a second voltage domain, said first voltage domain operating with a first voltage supply providing a first voltage level and a common voltage level and said second voltage domain operating with a second voltage supply providing a second voltage level and said common voltage level, said method comprising:

• employing data retention circuitry operating in said second voltage domain to operate in a transparent phase where a data value is subjected to a level shifting function and written into the data retention circuitry dependent on the input signal, and a latching phase where the data value written into the data retention circuitry during the transparent phase is retained irrespective of any change in the input signal during the latching phase;
• outputting said retained data value as said output signal;
• controlling the data retention circuitry in dependence on a received clock signal to operate in said transparent phase during a first phase of the clock signal and to operate in said latching phase during a second phase of the clock signal;
• writing, during the transparent phase, said data value into said data retention circuitry by controlling a voltage of at least one internal node of the data retention circuitry dependent on the input signal;
• and
• employing contention mitigation circuitry, during said transparent phase, to reduce a voltage drop across at least one component within the data retention circuitry based on said input signal, thereby assisting said writing step in altering the voltage of said at least one internal node during the transparent phase.

An integrated level shifting latch circuit for receiving an input signal in a first voltage domain and generating an output signal in a second voltage domain, said first voltage domain operating with a first voltage supply providing a first voltage level and a common voltage level and said second voltage domain operating with a second voltage supply providing a second voltage level and said common voltage level, said integrated level shifting latch circuit comprising:

• data retention means for operating in said second voltage domain and for operating in a transparent phase where a data value is subjected to a level shifting function and written into the data retention means dependent on the input signal, and a latching phase where the data value written into the data retention means during the transparent phase is retained irrespective of any change in the input signal during the latching phase, and that retained data value forms said output signal;
• control means for receiving a clock signal and for controlling the data retention means to operate in said transparent phase during a first phase of the clock signal and to operate in said latching phase during a second phase of the clock signal;
• writing means for writing, during the transparent phase, said data value into said data retention means by controlling a voltage of at least one internal node of the data retention means dependent on the input signal;
• and
• contention mitigation means for receiving said input signal and, during said transparent phase, for reducing a voltage drop across at least one component within the data retention means, thereby assisting said writing means in altering the voltage of said at least one internal node during the transparent phase.