Systems and methods for DSP block enhancement

Multiplier circuitry comprising:

• a first multiplier module;
• a second multiplier module comprising:
• a first component multiplier of the second multiplier module;
• and
• a second component multiplier of the second multiplier module;
• and
• selection circuitry configured to provide, to the second component multiplier of the second multiplier module, an input signal from a group consisting of an input signal to the first component multiplier of the second multiplier module, an input signal to the first multiplier module, a low logical state signal vector and a high logical state signal vector.

A method for multiplying a number AB and a number CD, the method comprising:

• computing a partial product AD based on multiplying a component A of the number AB and a component D of the number CD, wherein the component A comprises a subcomponent AH and a subcomponent AL, and wherein computing the partial product AD comprises:
• multiplying the component D and the subcomponent AL using a first multiplier circuitry of a plurality of multiplier circuitries
• multiplying the component D and the subcomponent AH the using a first multiplier module of a second multiplier circuitry of the plurality of multiplier circuitries;
• and
• computing a partial product BC based on multiplying a component C of the number CD and a component B of the number AB, wherein the component C comprises a subcomponent CH and a subcomponent CL, and wherein computing the partial product BC comprises:
• multiplying the component B and the subcomponent CL using a third multiplier circuitry of the plurality of multiplier circuitries;
• and
• multiplying the component B and the subcomponent CH the using a second multiplier module of the second multiplier circuitry of the plurality of multiplier circuitries.