Transactional memory that supports put and get ring commands
AssigneeNetronome Systems, Inc.
InventorGavin J. Stark
Life of this patent
Estimating the term…
Abstract
A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).
Claims22
A transactional memory, comprising:
- a memory unit that stores a ring of buffers, wherein one of the buffers is a tail buffer;
- and
- a ring buffer control circuit that receives a put into ring command, wherein the ring buffer control circuit does not have an instruction counter that it uses to fetch instructions from any memory, wherein the ring buffer control circuit comprises:
- a memory access portion coupled to read from and write to the memory unit;
- and
- a ring operation portion, wherein the ring operation portion:
- 1) stores and maintains a tail pointer so that the tail pointer points to the tail buffer of the ring, 2) in response to the receiving of the put into ring command uses the tail pointer to determine an address, and 3) supplies the address to the memory access portion such that the memory access portion uses the address to write to the tail buffer of the ring.
A transactional memory, comprising:
- a memory unit that stores a ring of buffers, wherein one of the buffers is a tail buffer and wherein another of the buffers is a head buffer;
- and
- a ring buffer control circuit adapted to receive a ring command, wherein the ring buffer control circuit does not have an instruction counter that it uses to fetch instructions from any memory, wherein the ring buffer control circuit comprises:
- a memory access portion coupled to read from and write to the memory unit;
- and
- a ring operation portion, wherein the ring operation portion maintains a tail pointer and a head pointer, wherein the ring operations buffer in response to the receiving of the ring command causes the memory access portion to access a buffer of the ring and to adjust either the tail pointer or the head pointer.
A method comprising:
- (a) storing a ring of buffers in a memory unit of a transactional memory, wherein the ring of buffers includes a head buffer and a tail buffer;
- (b) maintaining a tail pointer and a head pointer in a first stage of a pipeline of the transactional memory;
- (c) receiving a put into ring command from a bus and onto the transactional memory;
- (d) in the first stage of the pipeline using the head pointer and the tail pointer to determine if the ring is full;
- and
- (e) if the ring is determined to be not full in (d) then using the tail pointer to write a value into the tail buffer, wherein the writing of the value is performed by a stage of the pipeline other than the first stage, wherein the pipeline is clocked by a clock signal, and wherein the first stage processes a different command each cycle of the clock signal.
Dependencies are inferred from the claim text.