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US 9,069,563 B2Granted
Reducing store-hit-loads in an out-of-order processor
AssigneeInternational Business Machines Corporation
InventorsBrian R. Konigsburg, David S. Levitan, Brian R. Mestan, David Mui
Life of this patent
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Abstract
A technique for reducing store-hit-loads in an out-of-order processor includes storing a store address of a store instruction associated with a store-hit-load (SHL) pipeline flush in an SHL entry. In response to detecting another SHL pipeline flush for the store address, a current count associated with the SHL entry is updated. In response to the current count associated with the SHL entry reaching a first terminal count, a dependency for the store instruction is created such that execution of a younger load instruction with a load address that overlaps the store address stalls until the store instruction executes.
Claims20
A method for reducing store-hit-loads in an out-of-order processor, the method comprising:
- storing a store address of a store instruction associated with a store-hit-load (SHL) pipeline flush in an SHL entry;
- in response to detecting another SHL pipeline flush for the store address, incrementing a current count associated with the SHL entry;
- in response to the current count associated with the SHL entry reaching a first terminal count, creating a dependency for the store instruction such that execution of a younger load instruction with a load address that overlaps the store address stalls until the store instruction executes;
- and
- in response to the current count associated with the SHL entry reaching a second terminal count different from the first terminal count, removing the dependency for the store instruction such that execution of the younger load instruction does not stall;
- wherein the current count starts at zero, wherein the first terminal count is greater than zero, and wherein the second terminal count is greater than the first terminal count.
3 more elements
An out-of-order processor, comprising:
- a load-store unit;
- an instruction fetch unit coupled to the load-store unit, wherein the instruction fetch unit is configured to:
- store a store address of a store instruction associated with a store-hit-load (SHL) pipeline flush in an SHL entry;
- and
- in response to detecting another SHL pipeline flush for the store address, increment a current count associated with the SHL entry;
- and
- an instruction decode unit coupled to the instruction fetch unit, wherein the instruction decode unit is configured to:
- in response to the current count associated with the SHL entry reaching a first terminal count:
- create a dependency for the store instruction such that execution of a younger load instruction with a load address that overlaps the store address stalls until the store instruction executes, wherein the instruction decode unit creates the dependency for the store instruction in response to the instruction fetch unit marking the store instruction as an SHL risk and the instruction fetch unit is further configured to:
- in response to the current count associated with the SHL entry reaching a second terminal count different from the first terminal count, refrain from marking a subsequent fetched instruction with the store address as an SHL risk such that the instruction decode unit does not create a dependency for the store instruction and the execution of the younger load instruction does not stall;
- wherein the current count starts at zero, wherein the first terminal count is greater than zero, and wherein the second terminal count is greater than the first terminal count.
8 more elements
An instruction fetch unit for an out-of-order processor, the instruction fetch unit comprising:
- a circuit configured to:
- store a store address of a store instruction associated with a store-hit-load (SHL) pipeline flush in an SHL entry of a SHL data structure;
- in response to detecting a subsequent SHL pipeline flush for the store address, increment a current count associated with the SHL entry;
- in response to the current count associated with the SHL entry reaching a first terminal count, mark each subsequently fetched instruction with the store address as an SHL risk to facilitate creation of a dependency for each subsequently fetched instruction with the store address by an instruction dispatch unit;
- and
- in response to the current count associated with the SHL entry reaching a second terminal count different from the first terminal count, refrain from marking another subsequently fetched instruction with the store address as an SHL risk;
- wherein the current count starts at zero, wherein the first terminal count is greater than zero, and wherein the second terminal count is greater than the first terminal count.
4 more elements
A non-transitory machine readable medium storing a design structure comprising:
- a store-hit-load (SHL) data structure;
- and
- instructions that execute to implement functions of a hardware circuit coupled to the SHL data structure, wherein the circuit is configured to:
- store a store address of a store instruction associated with an SHL pipeline flush in an SHL entry of the SHL data structure, wherein the store address is an effective address;
- in response to detecting a subsequent SHL pipeline flush for the store address, increment a current count associated with the SHL entry;
- in response to the current count associated with the SHL entry reaching a first terminal count, mark each subsequently fetched instruction with the store address as an SHL risk to facilitate creation of a dependency for each subsequently fetched instruction with the store address such that execution of a younger load instruction with a load address that overlaps the store address stalls until the store instruction executes;
- and
- in response to the current count associated with the SHL entry reaching a second terminal count different from the first terminal count, refrain from marking another subsequently fetched instruction with the store address as an SHL risk;
- wherein the current count starts at zero, wherein the first terminal count is greater than zero, and wherein the second terminal count is greater than the first terminal count.
6 more elements
Dependencies are inferred from the claim text.